CMPEN 471   Logical Design of Digital Systems

Fall 2009

Instructor: Kyusun Choi Teaching Assistant: Adwait Jog Laboratory: Textbook: References: CSE471 Web Page:   Pre-requisite:  Exams:
Exam I Sep. 22, 2009, 8:15pm - 9:50pm, in room 73 Willard
Exam II Oct. 27, 2009, 8:15pm - 9:50pm, in room 73 Willard
Final Exam Date, time, and place to be announced
 
Homeworks:

VHDL Design Projects:

Pop Quiz:

Grading Policy:
 
Exam 1  15%
Exam 2  15%
Final 20%
Homeworks 15%
VHDL Projects 25%
Quiz 10%



Course Outline:
 
Weeks Contents Textbook Chapter
1 Modern Digital Design & CAD Tools: VHDL MZ 3
2 Combinational Circuit Analysis & Optimization HP 5
1 Optimum Multiple-Output Circuit Design HP 6
1 Optimal Function Implementation in CMOS, nMOS, & TTL Technologies HP 4, 7
1 Multilevel Design & Complex Functions HP 8
1 Sequential Circuit Analysis HP 9
2 Synchronous Sequential Circuit Design and Optimization HP 10, MZ 5
1 Incompletely Specified Sequential Circuits HP 13
1 Level Mode Circuit Design and Optimization HP 14, MZ 12
1 Test Generation for VLSI HP 15, MZ 10, 11
1 Complex System Design and Implementation MZ 7
1 Examinations