1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1)

Jan 10th 2010, Bangalore India

Held in conjunction with HPCA-16


Advanced Program is available on this link.


Organizing Chairs:

Ravi Iyer                    Intel Labs                                ravishankar.iyer@intel.com

Ramesh Illikkal          Intel Labs                                ramesh.g.illikkal@intel.com

Raj Yavatkar               Intel                                         raj.yavatkar@intel.com


Computing platforms are getting smaller (e.g. handheld devices), richer (e.g. visual computing applications) and broader (i.e. reaching the masses via smartphones and other embedded devices). This trend is made possible by System-on-Chip (SoC) architectures that combine high performance, ultra-low power general-purpose cores along with a wide spectrum of domain-specific accelerators or Intellectual Property (IP) blocks. With the recent introduction of general-purpose compute cores such as Intel Atom processor, these platforms have the potential to run a much broader range of applications than ever before. The goal of this workshop is to bring together academic researchers and industry practitioners to discuss future SoC architectures, accelerators and workloads.  The research challenges in SoC platforms are multi-fold, including: (a) providing rich functionality and high performance while maintaining ultra-low power, (b) attempting to cover a broad range of applications that can be migrated from mainstream platforms to SoC devices, (c) enabling a modular architecture and design environment that improves time-to-market and (d) providing a rich software programming environment that eases the challenge of developing applications on a heterogeneous architecture consisting of general-purpose cores as well as specialized accelerators. 


Below is the proposed list of topics for the workshop.  Topics include, but are not restricted to, the following:


o   Novel SoC Architectures

o   Ultra-Low Power Core Microarchitectures

o   Heterogeneous Architectures and Multi-core SoCs

o   Fabrics / Network-on-chip

o   Cache/Memory Hierarchies

o   HW Support for Programmability and Modularity

o   Automated Design Environments

o   Simulation / Emulation Methodologies

o   Emerging Workloads

o   New Workloads (e.g. Visual computing examples such as Augmented Reality, Muli-modal interfaces, etc)

o   Workload Analysis for optimization and acceleration

o   Workload Partitioning between Cores and Accelerators

o   Performance Monitoring and Evaluation

o   Case Studies of SoC applications

o   Novel Accelerator Designs

o   Specialized Accelerator Architectures and Designs

o   Domain-Specific Programmable/Configurable Accelerators

o   Accelerator Interfaces for Programmability

o   Development Environments for Accelerator Design

o   System-Level integration of Accelerators

o   SoC Systems Software

o   Modular Systems Software

o   Heterogeneous Programming Languages and Environments

o   Application Development Environments

o   Runtime Libraries and Environments


Submission Guidelines:


Interested authors are encouraged to submit extended abstracts (1 - 2 pages) or short papers (6 pages) by email to the organizing chairs (Ravi Iyer, Ramesh Illikkal and Raj Yavatkar). The deadline for submission is Oct 16th (by midnight in US PST zone). Final (short) papers will be due on Dec 7th 2009 and will be printed in a workshop proceedings made available to the workshop attendees.


Important Dates:

Abstract / Paper Submission

Oct 16th 2009

Author Notification

Oct 25th 2009

Final Paper Submission

Dec 7th 2009


Jan 10th 2010