The challenges in fabricating transistors with diminutive feature sizes in the nanometer regimes have resulted in significant variations in key transistor parameters, such as transistor channel length, gate-oxide thickness, and threshold voltage. This manufacturing variability can cause significant performance and power deviations from nominal values in identical hardware designs. Designing for the worst case scenario may no longer be a viable solution, especially when the variability encountered in the new process technologies becomes very significant and causes substantial percentage deviations from the nominal values. Increasing cost sensitivity in the embedded system design methodology makes designing for the worst case infeasible. Further, worst-case analysis without taking the probabilistic nature of the manufactured components into account can also result in an overly pessimistic estimation in terms of performance. As a result, a shift in the design paradigm, from today’s worst-case deterministic design to statistical or probabilistic design, is critical for deep sub-micron VLSI design.
The goal of the
project includes:
- EDA solutions: developing design automation techniques to perform statistical analysis and variation-aware synthesis for nanometer VLSI systems.
- Circuit/Architecture solutions: developing design techniques for variation tolerant circuits/architecture.
Project Sponsors:
- NSF: CAREER: Process Variation Aware Embedded MPSoC
Synthesis
(PI: Yuan Xie)
- SRC : Statistical Behavioral Synthesis for Nanometer VLSI Chips
(PI:
Students:
Selected Publications:
- Feng Wang, Andres Takach, Yuan Xie. " Variation Aware Resource Binding and Scheduling ."; in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)Jan. 2009.
- Yibo Chen, Yuan Xie. "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches."; in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)Jan. 2009.
- Feng Wang, Guangyu Sun, Yuan Xie. "A Variation Aware High Level
Synthesis Framework."; in Proceedings of Design Automation and Test in Europe (DATE), Mar. 2008.
- Feng Wang, Xiaoxia Wu, Yuan Xie. "Variability-Driven Module Selection with Joint Design Time Optimization and
Post-Silicon Tuning."; To appear in Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2008.
Best Paper Award
- Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie, N.
Vijaykrishnan.
"Variation-aware Task
Allocation and Scheduling
for MPSoC." Proc. of Intl. Conf. on Computer Aided
Design
(ICCAD), pp.138-149, Nov. 2007
- S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. "FPGA
Routing Architecture Analysis Under Variations."
Proceedings of International Conference on Computer Design
(ICCD), pp. 152-157, Oct. 2007.
- Feng Wang, Yuan Xie, and Hai Ju. "A Novel Criticality Computation
Method in Statistical Timing Analysis." Proceedings
of IEEE International Conference on Design Automation and Test in
Europe (DATE), pp. 1611-1616, 2007.
- Wei-lun Hung, XiaoxiaWu, Yuan Xie. "Guaranteeing Performance Yield in High-Level Synthesis." Proceedings of Interna tional Conference on Computer Aided Design (ICCAD), pp.303-309, Nov. 2006. Best Paper Award Nomination