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A. JOURNALS

• [J1]. R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin. "Modeling Soft Errors at Device and Logic Level for Combinational Circuits." To appear in IEEE Transactions on Dependable and Secure Computing (TDCS).
  

• [J2]. Shengqi Yang, W. Wolf, Yuan Xie, N. Vijaykrishnan. "A New Methodology for Reliability-Aware Low-Power Design."; To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
  

• [J3]. S. Srinivasan, R. Krishnan, P. Mangalagiri, Yuan Xie, and N. Vijaykrishnan. "Towards Increasing FPGA Lifetime."; To appear in IEEE Transactions on Dependable and Secure Computing (TDCS).
  
  
• [J4]. Feng Wang, Mike Debole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. "On-chip Bus Thermal Analysis and Optimization."; To appear in IET Computer and Digital Techniques.
  
  
• [J5]. Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. "Design Space Exploration for Three- Dimensional Cache."; To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
  
  
• [J6]. Chang-hong Lin, Yuan Xie, and W.Wolf. "Code Compression for VLIW Embedded Systems Using a Self-Generating Table."; IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 10., Oct. 2007
  
  
• [J7]. Yuan Xie, W.Wolf, and H. Lekatsas. "Decompression Unit Design for VLIW Embedded Processors."; IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 8, pp.975-980, Aug. 2007.
  
  
• [J8]. Gabriel Loh, Yuan Xie, and Bryan Black. "Processor Design in Three-Dimensional Die-Stacking Technologies."[PDF]; IEEE Micro, Vol. 27. No. 3, pp.31-48, May/June 2007.
  
  
• [J9]. Yuan Xie, Lin Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin."Reliability-Aware Co-synthesis for Embedded Systems." [PDF]; Journal of VLSI Signal Processing, March 2007.
  
  
• [J10]. Yuan Xie, Wei-lun Hung. "Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems- on-Chip (MPSoC) Design." [PDF]; Journal of VLSI Signal Processing, Vol. 45, No. 3, pp.177-189, December 2006.
  
  
• [J11]. Yuan Xie, Gabriel Loh, Bryan Black, and Kerry Bernstein. "Design Space Exploration for 3D Architecture."[PDF]; ACM Journal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006.
  
  
• [J12]. N. Vijaykrishnan and Yuan Xie. "Reliability Concerns in Embedded System Designs." [PDF]; IEEE Computer, Vol. 39, No. 1, pp.118-120, January 2006.
  
  
• [J13]. Yuan Xie, W.Wolf, and H. Lekatsas. "Code Compression Using Variable-to-fixed Coding."[PDF] ; IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 14. No. 5, pp.525-536, January. 2006.
  
  
• [J14]. Yuan Xie, Jiang Xu, W.Wolf. "Augmenting Platform-based Design with Synthesis Tools."; Journal of Circuits, Systems and Computers, Vol. 14. No. 5, pp.525-536, April. 2003

B. REFEREED CONFERENCE PAPERS

• Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie. “Leveraging 3D PCRAM Technologies to Reduce Checkpoint Overhead for Future Exascale Systems.” To appear in Proceedings of International Conference on High Performance Computing, Networking, Storage and Analysis (SC). 2009. (22% acceptance rate(59/261))

• Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. “Hybrid Cache Architecture with Disparate Memory Technologies.” Proceedings of International Symposium on Computer Architecture (ISCA), pp.34-45, June. 2009 (20% acceptance rate (43/210))

• Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. “Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization.” (PDF) Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333. April. 2009. (23%, 226/965).

• Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. “Power and Performance of Read-write aware hybrid caches with non-volatile memories.” (PDF) Proceedings of Design Automation and Test in Europe (DATE), pp. 737-742. April. 2009.

• Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. “A Novel MRAM Stacking Architecture for Chip-multiprocessors (CMP).” Proceedings of High Performance Computer Architecture (HPCA), pp. 239-249. Feb. 2009. (19% acceptance rate(34/185))

• Xiangyu Dong and Yuan Xie. “System-level Cost Analysis and Design Exploration for 3D ICs.” Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. Best Paper Award Nomination. (32% acceptance rate(116/355))

• Feng Wang, Andres Takach, and Yuan Xie. “Variation-Aware Resource Sharing and Binding in Behavioral Synthesis.” Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).

• Yibo Chen and Yuan Xie. “Tolerating Process Variations in High-Level Synthesis Using Transparent Latches.” Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355))

• P. Mangalagiri, S. Bae, R. Krishnan, Yuan Xie, N. Vijaykrishnan. “Thermal-Aware Reliability Analysis for Platform FPGAs ” Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 722-727, Nov. 2008. (122 out of 458 submissions, 27% acceptance rate).

• Xiaoxia Wu, Yibo Chen, Krish Chakrabarty, and Yuan Xie. “ Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs.” Proceedings of International Conference on Computer Design (ICCD), pp.212-218 Oct. 2008

• D. Park, S. Eachempati, R. Das, A. Mishra, Yuan Xie, V. Narayanan, C. Das, "MIRA: A Multi-layer On Chip Interconnect Router Architecture"; To appear in the Annual International Symposium on Computer Architecture (ISCA), June 2008. (37 papers accepted out of 259 submissions. 14% acceptance rate)
  
  
• Feng Wang, Guangyu Sun, Yuan Xie. "A Variation Aware High Level Synthesis Framework"; To appear in Proceedings of Design Automation and Test Conference (DATE), Marh. 2008 .
  
  
• Feng Wang, Xiaoxia Wu, Yuan Xie. "Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning."; To appear in Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2008. Best Paper Award (100 regular papers accepted among 350 submissions (28.5%)).
  
  
• Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan. "Variation-aware Task Allocation and Scheduling for MPSoC."[PDF] Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 598-603, Nov. 2007. (139 out of 510 submissions (27%).
  
  
• Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. "Scan Chain Design for Three-dimensional (3D) ICs." Proceedings of International Conference on Computer Design (ICCD), pp.208-214,Oct. 2007.
  
  
• S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. "FPGA Routing Architecture Analysis Under Variations." To appear in Proceedings of International Conference on Computer Design (ICCD), Oct. 2007.
  
  
• J. Kim, C. Nicopoulos, D. Park, R. Das, Yuan Xie, N. Vijaykrishnan, C. Das. "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures." [PDF]; Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 138-149, June 2007. (46 papers accepted out of 204 submissions. 23% acceptance rate)
  
  
• Alex K. Jones, Steven Levitan, Rob A. Rutenbar, and Yuan Xie. "Collaborative VLSI-CAD Instruction in the Digital Sandbox." [PDF]; Proceedings of IEEE International Conference on Microelectronic Systems Education, pp. 141-142, June 2007.
  
  
• Feng Wang, Yuan Xie, and Hai Ju. "A Novel Criticality Computation Method in Statistical Timing Analysis."[PDF]; Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1611-1616, April 2007. (208 papers accepted out of 933 submissions. 22% acceptance rate)
  
  
• Y. Wang, H. Luo, K. He, R. Luo, Yuan Xie, and H. Yang. "Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation." [PDF]; Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 546-551, April 2007. (208 papers accepted out of 933 submissions. 22% acceptance rate)
  
  
• R. Krishnan, R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Variation Impact on SER of Combinatorial Circuits." [PDF]; Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 911-916, March 2007. (93 papers accepted out of 292 submissions. 31% acceptance rate)
  
  
• A. Mupid, M. Mutyam, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Variation Analysis of CAM Cells." [PDF]; Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 333-338, March 2007. (93 papers accepted out of 292 submissions. 31% acceptance rate)
  
  
• H. Luo, Y. Wang, K. He, R. Luo, H. Yang, Yuan Xie. "Modeling of PMOS NBTI Effect Considering Temperature Variation." [PDF]; Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 139-144, March 2007. (93 papers accepted out of 292 submissions. 31% acceptance rate)
  
  
• Feng Wang, Yuan Xie, R. Rajaraman, B. Vaidyanathan. "Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model."[PDF]; Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 165-170, Jan. 2007. (141 papers accepted out of 432 submissions. 32% acceptance rate)
  
  
• Balaji Vaidyanathan, W-L. Hung, Feng Wang, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Architecting Microprocessor Components in 3D Design Space." [PDF]; Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 103-108, Jan. 2007. (141 papers accepted out of 432 submissions. 32% acceptance rate)
  
  
• Balaji Vaidyanathan, Yuan Xie, N. Vijaykrishnan, R. Luo. "Leakage Optimized DECAP Design for FPGAs." [PDF] Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 560-563, Dec. 2006.
  
  
• Wei-lun Hung, Xiaoxia Wu, Yuan Xie. "Guaranteeing Performance Yield in High-Level Synthesis."[PDF] Proceedings of International Conference on Computer Aided Design (ICCAD), pp.303-309, Nov. 2006. Best paper Award Nomination.(130 papers accepted out of 537 submissions. 24% acceptance rate).
  
  
• Qian Ding, R. Luo, H. Wang, H. Yang and Yuan Xie. "Modeling the Impact of Process Variation on Critical Charge Distribution." [PDF]; Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 243-237, Sept. 2006. (58 regular papers accepted out of 177 submissions. 31% acceptance rate)
  
  
• Balaji Vaidyanathan and Yuan Xie. "Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression." [PDF];Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 93-97, Sept. 2006. (58 papers accepted out of 177 submissions. 31% acceptance rate)
  
  
• Xiaoxia Wu, Feng Wang, and Yuan Xie."Analysis of Subthreshold Finfet Circuit for Ultra-low Power Design." [PDF]; Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 91-93, Sept. 2006.
  
  
• S. Srinivasan, M. Prasanth, S. Karthink, Yuan Xie, N. Vijaykrishnan. "FLAW: FPGA Lifetime Awareness."[PDF] Proceedings of the 43rd Design Automation Conference (DAC), pp. 630-635, July. 2006. (209 papers accepted out of 865 submissions. 24% acceptance rate)
  
  
• F. Li,C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, M. Kandemir. "Design and Management of 3D Chip Multiprocessors using Network-in-memory." [PDF 670KB]; Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)
  
  
• Feng Wang, Yuan Xie. "An Accurate and Efficient Model of Electrical Masking Effect for Soft Errors in Combinatorial Logic." [PDF]Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.
  
  
• B. Vaidyanathan, Yuan Xie, N. Vijaykrishnan. "Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits." [PDF]; Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.
  
  
• R. Ramanarayanan, R. Krishnan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin."Temperature and Voltage Scaling Effects on Electrical Masking."[PDF]; Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006.
  
  
• Wei-lun Hung, G. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors." [PDF];Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 98-104, March. 2006. (93 papers accepted out of 256 submissions. 36% acceptance rate)
  
  
• Feng Wang, Yuan Xie, N. Vijaykrishnan and M. J. Irwin. "On-chip Bus Thermal Analysis and Optimization." [PDF];Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 850-855, March 2006. (233 papers accepted out of 834 submissions. 28% acceptance rate)
  
  
• Feng Wang, Yuan Xie, K. Bernstein and Y. Luo. "Dependability Analysis of Nano-scale FinFET Circuits." [PDF];Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 399-404, March 2006.
  
  
• M. Mutyam, M. Eze, N. Vijaykrishnan, Yuan Xie. "Delay and Energy Efficient Data Transmission for On-Chip Buses." [PDF]; Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 355-360, March 2006.
  
  
• S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. "Reliability-Aware SOC Voltage Islands Partition and Floorplan." [PDF];Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 343-348, March 2006.
  
  
• O. Ozturk, F. Wang, M. Kandemir, Yuan Xie. "Optimal Topology Exploration for Application-Specific 3D Architectures." [PDF]; Proceedings of Asia and South Paci¯c Design Automation Conference (ASP-DAC), pp. 390-395, Jan. 2006. (135 papers accepted out of 432 submissions. 31% acceptance rate)
  
  
• Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Yuan Xie, M. J. Irwin."SEAT-LA: A Soft Error Analysis tool for Combinational Logic." [PDF]; Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers (88 out of 328 submissions))
  
  
• T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C. R. Das. "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks." [PDF 331KB]; Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers)
  
  
• R. Luo, H. Luo, H. Yang, Yuan Xie. "An Instruction Level Analytical Power Model for Designing Low Power SOC."[PDF] Proceedings of IEEE International Conference on ASICs, pp.1070-1073, Oct. 2005.
  
  
• T. Richardson and Yuan Xie. "Evaluation of Thermal-Aware Design Techniques for Microprocessors." [PDF];Proceedings of IEEE International Conference on ASICs, pp.62-65, Oct. 2005.
  
  
• W-L. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, N. Dhanwada, J. Conner. "Temperature-Aware Voltage Islands Architecting in System-on-Chip Design."[PDF];Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 689-696, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
  
  
• S. K. Narayanan, G. Chen, M. Kandemir, Yuan Xie. "Temperature-Sensitive Loop Parallelization for Chip Multiprocessors." [PDF 303KB]; Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 677-682, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
  
  
• Y-F. Tsai, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Three-Dimensional Cache Design Exploration Using 3DCacti." [PDF]; Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 519-524, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
  
  
• D. Hostetler and Yuan Xie. "Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters." [PDF]; Proceedings of IEEE International Symposium on VLSI (ISVLSI), pp. 186-191, May. 2005.
  
  
• W-L. Hung, Yuan Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin "Thermal-Aware Floorplanning Using Genetic Algorithms." [PDF 167KB]; Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 634-639, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
  
  
• S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. "An ILP Formulation for Reliability-Oriented High-Level Synthesis." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
  
  
• S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. "Reliability-Centric Hardware/Software Co-design." Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
  
  
• S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. "Reliability-centric High-level Synthesis." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1258-1263, March 2005. ( 176 papers accepted out of 825 submissions. 21% acceptance rate)
  
  
• S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. "Power Attack Resistant Crypto Design: A Dynamic Voltage and Frequency Switching Approach." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 64-69, March 2005. ( 21% acceptance rate)
  
  
• Wei-lun Hung, Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. "Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 898-899, March 2005.
  
  
• Y-F Tsai, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Leakage-Aware Interconnect for On-Chip Network."[PDF]; Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 230-231, March 2005.
  
  
• J.Conner,Yuan Xie, M. Kandemir, R. Dick, G. Link."FD-HGAC: A Hybrid Heuristic/Genetic Algorithm Hard- ware/Software Co-synthesis Framework with Fault Detection."[PDF] Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)., pp. 709-712, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))
  
  
• S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie. "Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies." [PDF] Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)., pp. 539-544, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))
  
  
• Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin, Yuan Xie. "Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty." [PDF] Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 374-379, Jan. 2005. (97 regular papers accepted out of 352 submissions (28%)).
  
  
• S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie. "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits." [PDF] Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 165-170, Jan. 2005. (97 regular papers accepted out of 352 submissions (28%)).
  
  
• S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Yuan Xie, M. J. Irwin. "Improving Soft-error Tolerance of FPGA Configuration Bits." [PDF 307KB]; Proceedings of International Conference on Computer Aided Design (ICCAD), Nov. 2004. (24% acceptance rate).
  
  
• W-L Hung, C. Addo-Quaye, T. Theocharides, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. "Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture." [PDF 350KB]; Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 430-437, Oct. 2004. (84 out of 226 submissions, 37% acceptance rate.)
  
  
• Yuan Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin."Reliability-aware Cosynthesis for Embedded Systems." [PDF 443 KB]; Proceedings of IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 41-50, Sept. 2004.
  
  
• W-L. Hung,Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. "Total Power Optimization Through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing." [PDF 184KB]; Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2004), pp. 144-149, Aug. 2004. 34% acceptance rate)
  
  
• W. Xu, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Design of a Nanosensor Array Architecture." Proceedings of Great Lakes Symposium on VLSI(GLSVLSI), pp. 298-303, Apr. 2004. (23 full papers accepted out of 235 submissions, 10% rate)
  
  
• V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "The Effect of Threshold Voltages on the Soft Error Rate." [PDF 304KB]; Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 503-508, Mar. 2004. (49 papers accepted out of 148 submissions, 33%)
  
  
• C-H. Lin, W. Wolf, and Yuan Xie. "LZW-based Code Compression for VLIW Embedded Systems." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 76-81, Feb. 2004. (181 papers accepted out of 780 submissions (23%))
  
  
• Yuan Xie. "Analysis of Two Code Compression Algorithms for Embedded Systems." Proceedings of International Conference on ASIC (ASICON), pp. 773-776. Oct. 2003.
  
  
• Yuan Xie, Wayne Wolf, H. Lekatsas. "Code Compression Using Arithmetic Coding Based Variable-to-fixed Coding." [PDF] Proceedings of Data Compression Conference(DCC 2003), pp. 382-391, Mar. 2003.
  
  
• Yuan Xie, W.Wolf, and H. Lektasas. "Profile-driven Code Compression." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 76-81, Mar. 2003. (152 out of 590 submissions (25%))
  
  
• Yuan Xie, W. Wolf, and H. Lektasas. "Code Compression for VLIW Using Variable-to-fixed Coding."[PDF];Proceedings of Fifteenth International Symposium on System Synthesis (ISSS 2002), pp. 138-143, Oct. 2002. (24 out of 71 submissions (33%))
  
  
• Yuan Xie, W. Wolf, and H. Lektasas. "A Code Decompression Architecture for VLIW Processors." [PDF] Proceedings of the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. (29 out of 144 submissions, 20% acceptance rate)
  
  
• Yuan Xie, W.Wolf, and H. Lektasas. "Compression Ratio and Decompression Overhead Tradeoffs in Code Compression
  for VLIW Architectures."[PDF] Proceedings of the Fourth International Conference on ASIC (ASICON). pp.337-340. 2001. Best Paper Award.
  
  
• Yuan Xie, W. Wolf. "ASICosyn: Co-Synthesis of Coditional Task Graphs with Custom ASICs."[PDF] Proceedings of the Fourth International Conference on ASIC (ASICON).
  
  
• Yuan Xie, W. Wolf. "Allocation and Scheduling of Conditional Task Graphs in Co-synthesis." [PDF] Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 620-625, Mar. 2001. (81 full papers out of 300 submissions (27%))
  
  
• Yuan Xie, Hua Lin, Zhao Wu, W. Wolf. "CAD Techniques for Multimedia System Design." Proceedings of Synthesis and System Integration of MIxed Technologies (SASIMI), Mar. 2000.
  
  
• Yuan Xie and Wayne Wolf. "Co-synthesis with Custom ASICs." [PDF] Proceedings of the Asia South Pacific Design Automa- tion Conference (ASP-DAC), pp. 129-134, Jan. 2000.

C. BOOK CHAPTERS

• Degalahal, V., R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. "Effect of Power Optimizations on Soft Error Rate." IFIP Series on VLSI-SoC. pp. 1-20, 2006. Edited by R. Reis. Springer.

• H. Luo, W. Wang, K. He, R. Luo, H. Yang, and Yuan Xie. "A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect." Integrated Circuits and System Design: Power and Timing Modeling, Optimization and Simulation. pp. 160-170, 2007. Edited by N. Azemard and L. Svensson. Springer.

D. PATENTS

• [1]. United States Patent. No.7,095,343. "Code Compression Algorithms and Architectures for Embedded Systems." Issued on August 22, 2006.