Low Power Design and Thermal-Aware Design Techniques

  Process scaling and aggressive performance improvements have resulted in power consumption becoming a first-order design criterion. For example, the latest Intel Pentium 4 processor (Prescott, 2004) has a power consumption of 103 Watts, almost four times larger than that of the Pentium III (1999). In addition to its clear impact on battery lifetime in portable embedded systems, processor power consumption has also become a primary constraint on workstation performance. Therefore, reducing power dissipation is a top priority in modern VLSI design.  

Selected publication in Low Power and Power-Aware Design:  

• D. Hostetler, Y. Xie. Adaptive Power Management in Software Radios using Resolution Adaptive Analog to Digital Converters, IEEE International Symposium on VLSI, 2005.
• Tsai, Y-F., N. Vijaykrishnan, Y. Xie, M. J. Irwin. Leakage-Aware Interconnect for On-Chip Network. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). Munich, Germany.
• W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin,Y. Tsai, "Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing", International Symposium on Low Power Electronics and Design (ISLPED)2004, Newport Beach, CA, August 2004

    Dramatic power consumption increase, smaller feature size, and higher packing density, result in higher power density; power density directly translates into heat; as a result, the temperature in modern high-performance VLSI circuits increases dramatically. The hotspot in a modern chip might have a temperature beyond 100 ^oC, while the intra-chip temperature differentials can be larger than 10~20^oC. High temperature can also have a dramatic impact on circuit performance, leakage power, reliability, and package cost.  Power-aware design alone is not able to address the temperature challenge, because  they do not directly target the spatial and temporal behavior of the operating temperature. Therefore, even though it is related to the power-aware design area, thermal-aware design itself is a distinct and important research area.

Selected publication in Thermal-Aware Design Techniques:

• W. Hung, G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada, and J. Conner, Temperature-Aware Voltage Islands Architecting in System-on-Chip Design, to appear in International Conference on Computer Design (ICCD) 2005.
• W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). Munich, Germany.
• W. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin. Thermal-Aware Floorplanning Using Genetic Algorithms. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED 2005). San Jose, CA.
• W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M. J. Irwin, " Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture", IEEE 22nd International Conference on Computer Design (ICCD 2004).

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