Workshop on Technology-Architecture Interaction: Emerging Technologies and their Impact on Computer Architecture

Held in conjunction with 43^rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43)

December 5^th, Sunday (8:30am – 5pm)

Klaus Advanced Computing Building

Georgia Tech, Atlanta

The goal of the Workshop on Emerging Technologies is to provide an in-depth look at the new architectures/techniques enabled by emerging technologies from an ‘architects toolbox’ point of view. Expert speakers from various companies and academic research labs will discuss their insights on emerging micro-architectures enabled by the availability of new technologies.

Topics to be covered:

- Phase-Change Memory: Challenges and microarchitectural implications

- Magneto-resistive Random Access Memory

- 3D Integration: basics and microarchitectural implications

- Ultra-low Voltage design

- Energy efficiency and Reliability Outlook

Organizers:

- Eren Kursun (IBM)

- Norm Jouppi (HP Labs)

- Hsien-Hsin Lee (Gatech)

- Yuan Xie (Penn State University)

Tentative Schedule:

KEYNOTE by Dr. William Gallagher

Senior Manager - Exploratory Non-Volatile Memories

IBM Research

Abstract: Memory-storage systems today are serviced by a combination of SRAM, DRAM, FLASH, hard disk drives, and magnetic tape storage systems.  The use of so many technologies reflects the varying attributes – such as performance, power, and density – that each technology addresses well.  The degrees to which these are all well addressed have opened up opportunities for new technologies.   This talk will review some of these opportunities and discuss in some depth two emerging new technologies which IBM is pursing, magnetoresistive random access memory (MRAM) and phase change random access memory (PCRAM or PRAM).   Particularly for large systems, it looks like PCRAM could provide a very useful “storage class memory” to bridge the large performance gap between active memory technologies and storage technologies.

Session 1: (8:30am -10:00am)

Emerging Technologies Overview: Key Challenges and Opportunities

KEYNOTE: William Gallagher, IBM Research

Coffee Break: (10:00am – 10:30am)

Session 2: (10:30am – 12:00)

Emerging Memory Technologies

Microprocessor Memory Circuits

By Dr. Shih-lien Lu (Intel) 

A Frank Conversation Between a Device Engineer and An Architect: Case Studies in STT-RAM Research

By Prof. Yiran Chen (Univ. of Pittsburg)

MAAEMO: Modeling, Architecture, and Applications for Emerging Memory Technologies

By Prof. Yuan Xie (Pennsylvania State Univ.)

Lunch Break: (12:00-1:30pm)

Session 3: (1:30pm – 3:00pm)

3D Integration Technologies

3D Heterogeneous Interconnect Technologies for Nanoelectronics

By Prof. Muhannad Bakir (Gatech)

System Design in 3D

By Dr. Eren Kursun (IBM)

Architecture, design, and implementation of a 3D-IC many-core processor

Hsien-Hsin Lee (Gatech)

Coffee Break: (3:00pm – 3:30pm)

Session 4: (3:30pm – 5:00pm)

Optical Interconnect Technologies

Leveraging photonics for large-scale computer systems

By Dr. Frankie Liu and Dr. Michael O. McCracken (Oracle)

Photonics Implications for Networks and Memory Systems

By Dr. Nate Binkert (HP Labs)

Speakers’ Biography:

Dr. William Gallagher (IBM Research)

William J. Gallagher joined IBM Research in 1978 after receiving his B.S. in Physics summa cum laude from Creighton University (1974) and his Ph.D. in Physics from MIT. In his early years at IBM he worked on Josephson computer technology and later helped found and served as a Director of the IBM-AT&T-MIT-founded Consortium for Superconducting Electronics (CSE). Since 1995, Dr. Gallagher has been leading efforts at IBM to develop magnetic tunnel junctions into nonvolatile random access memories (MRAM), including joint development alliances with Infineon and with TDK. Currently he is senior manager of Quantum Computing and Exploratory Nonvolatile Memories at the IBM Thomas J. Watson Research Center where he oversees exploratory research and development in quantum computing, MRAM, and phase change memory.

Dr. Gallagher is a fellow of the IEEE and of the American Physical Society. He has served as Assistant to the Chairman of the APS Panel on Public Affairs, on the Executive Committee of the APS Forum on Physics and Society, on the Board of Directors of the Applied Superconductivity Corporation, on a number of university and government lab review panels. Dr. Gallagher has over 150 technical publications and holds sixteen U.S. patents.

Dr. Shih-Lien Lu (Intel)

Shih-Lien Lu is currently a Principal Engineer with the Microprocessor technology Labs of Corporate Technology Group, Intel Corporation at Hillsboro Oregon. He leads a team of researchers working on Microarchitecture techniques to extend Moore's Law. He received his BS in EECS from UC Berkeley, and MS and PhD both in CSE from UCLA. Prior to joining Intel in 1999, he worked on the MOSIS project at USC/ISI which provides research and education community VLSI fabrication services from 1984 to 1991. After MOSIS he was on the faculty of the ECE Dept. at Oregon State University. While at OSU, he received the College of Engineering Carter Award for outstanding and inspirational teaching in 1995 and the Engelbrecht Young Faculty Award in 1996.

Prof. Yiran Chen (University of Pittsburg)

Yiran Chen received B.S. and M.S. in EE from Tsinghua University, China and Ph.D. in ECE from Purdue University, W. Lafayette, IN. He was with Synopsys Inc., Sunnyvale, CA, where he developed the award-winning statistical static timing analysis EDA tool "PrimeTimeVX". He joined alterative technology group (then solid state drive group) of Seagate Technology in 2007, where he is working on the next-generation nonvolatile memory and solid state drive (SSD) controller. His research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power circuit design and computer architecture, emerging memory technologies and nano-scale reconfigurable computing system and sensor system. Dr. Chen has published more than 58 technical publications in refereed journals and conferences, has 57 pending US and international patents and 1 Seagate Trade Secret. His book: "Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing", will be published in 2011 by CRC Press.Dr. Chen serves as the Patent Review Board member of Seagate Memory Product Group (MPG) from 2007. He has been the Technical Program Committee Member, Track Chair, Session Chair of many international conferences, including ICCCAS, ASP-DAC, ASQED, DATE, VLSI Design, ICCAD, ISQED, ISLPED, FPL, FPT, ISCAS, etc. He has been reviewers for numerous journals and conferences. Dr. Chen received "The hot 100 products of 2006 - PrimeTimeVX" from EDN and the finalist of "Prestigious 2007 DesignVision Awards" from International Engineering Consortium (IEC). He also received "PrimeTimeVX - EDN 100 Hot Products Distinction" from Synopsys Inc. He got one best paper award and two best paper nominations from ISQED 2008, 2010 and 2005, respectively, one best paper award from ISLPED 2010, one best paper candidate (pending) from DATE 2010, and one best paper nomination (pending) from ASP-DAC 2011. His invention of Spintronic Memristor was interviewed and reported by IEEE Spectrum in Mar. 2009.

Prof. Yuan Xie (Pennsylvania State University)

Yuan Xie received the B.S. degree in electronic engineering from Tsinghua University, Beijing, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Princeton University in 1999 and 2002, respectively. He is currently Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. Before joining Penn State in Fall 2003, he was with IBM Microelectronic Division's Worldwide Design Center. Prof. Xie is a recipient of the National Science Foundation Early Faculty (CAREER) award, the SRC Inventor Recognition Award, IBM Faculty Award, and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems. His current research projects include: three-dimensional integrated circuits (3D ICs) design, EDA, and architecture; emerging memory technologies; low power and thermal-aware design; reliable circuits and architectures; and embedded system synthesis. He is currently Associate Editor for ACM Journal of Emerging Technologies in Computing Systems (JETC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), IEEE Design and Test of Computers, IET Computers and Digital Techniques (IET CDT).

Prof. Muhannad Bakir (Georgia Tech)

Muhannad S. Bakir received the B.E.E. degree (summa cum laude) from Auburn University, Auburn, AL, in 1999 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech) in 2000 and 2003, respectively. He was a senior research engineer at the Nanoelectronics Research Center at Georgia Tech from 2003-2010. He is the editor of a book entitled Integrated Interconnect Technologies for 3D Nanoelectronic Systems and is the author/coauthor of more than 60 journal publications and conference proceedings, 5 book chapters, 10 US patents, multiple invited presentations, and the presenter of 2 conference tutorials, including an invited tutorial on 3D technology at the 2007 International Solid-State Circuits Conference (ISSCC).

Dr. Eren Kursun (IBM Research)

Eren Kursun is a Research Staff Member at IBM Research T.J. Watson Center, she has been involved in research projects and test-sites focusing on power/temperature management and technology-aware design for microprocessor architectures. Dr. Kursun has published on energy-efficient and technology-aware microprocessor design; she received best paper award in IEEE International Conference on Computer Design and IEEE Micro Top Picks. She received her B.Sc. degree in Electrical and Electronics Engineering from Bogazici University; M.Sc. and Ph.D. degrees from University of California, Los Angeles.

Prof. Hsien-Hsin Lee (Georgia Tech)

Hsien-Hsin S. Lee is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He received his PhD degree in computer science and engineering from the University of Michigan at Ann Arbor. His main research interests include computer architecture, multiprocessors, low power VLSI, cyber security, 3D graphics, and 3D ICs (a different kind of 3D). Prior to joining academia, he was a senior processor architect at Intel Corporation, in both the product design teams (MD6) and the microprocessor research labs (MRL). During his tenure at Intel, he started working on logic verification and structural testing for P6S (Pentium Pro 200MHz). Then, he was heavily invovled in the evaluation of MMX in P-II for 3D games (being the first engineer who identified the notorious EMMS switching penalty in P-II but absent in PPMT that created a havoc in the entire industries), the definition of the first SSE instruction set, and the design of prefetch functionality for Katmai processor (P-III), and was responsible for publishing Intel's Geometry roadmap for 3D graphics. He co-authored the memory optimization and prefetch scheduling chapters in the Intel Architecture Software Optimization Reference Manual. He also worked on Microsoft's Direct3D 6.1, porting its 3D geometry pipeline using SSE ISA. In addition, he was involved in the early architecture planning of one of the first integrated CPU/GPU processors (Timna) prior to Y2K. In MRL, he studied the ILP limit and instruction reuse techniques for Itanium Processor Family. He later joined as the architecture manager of StarCore DSP Technology Center, a joint design center of Agere Systems and Motorola, Inc. In this job capacity, he led the architecture development of the StarCore SC-140e and a future high-frequency, deep-pipelined DSP for 3G infrastructure. At Georgia Tech, Dr. Lee leads the Microprocessor Architecture ReSearch (MARS) Lab at the School of ECE, nuturing an army of enthusiastic geeks into classy, seasoned researchers to carry out our mission and shake up the high-tech industry. Dr. Lee has co-authored 3 papers that won the Best Paper Awards in MICRO-33, CASES-2004 and IBM PAC2 and 3 papers nominated for the Best Paper Award in HPEC-07, FPL-07, and ICCAD-2009. He holds 4 U.S. patents in the area of memory subsystems and 3D graphics. Dr. Lee received the DoE Early CAREER PI Award in 2005, the 2006 ECE Outstanding Jr. Faculty Member Award at Georgia Tech, and the NSF CAREER Award in 2007. He is a member of Tau Beta Pi and a senior member of both the ACM and the IEEE.

Dr. Frankie Liu (Oracle)

Frankie Liu received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. At Oracle, Frankie designs analog and digital circuits in the VLSI Research Group. Prior to Oracle and Sun Microsystems, he was at Applied Materials, and also True Circuits. His interests include applied physics and mathematics.

Dr. Michael O. McCracken (Oracle)

Michael McCracken received his M.S. and Ph.D. degrees in Computer Science from The University of California at San Diego. Michael is currently a member of the computer architecture and performance research group in Oracle's Sun Labs. Michael has worked in performance analysis, modeling and simulation of large-scale systems, as well as performance optimization of large scale scientific workloads, collaborating with scientists at the San Diego Supercomputer Center while at UCSD.

Dr. Nathan Binkert (HP Labs)

Nathan Binkert is a Senior Research Scientist at HP labs where he is a member of the Exascale Datacenter project.  His current research lies in two areas: the design of systems that take advantage of new optical devices and large scale systems employing novel memory technologies. His broader research interests lie at the intersection of computer architecture, operating systems, and networking. Binkert received his PhD and MSE in Computer Engineering and his BSE in Electrical Engineering all from The University of Michigan.