Tutorial: Integrated Multi-core Modeling

Co-located with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)

Westin New York at Times Square, New York City,

1:30 PM to 5:45 PM, December 13(Sunday), 2009

ABSTRACT: Pre-silicon function and performance modeling in the 21st century has quickly evolved, out of technology-driven necessity, into an integrated modeling art or science. No longer is it meaningful for architects to study performance (IPC) sensitivities in isolation, while product quality metrics like power, temperature and reliability are modeled only in late-stage design. With cycle-accurate performance models augmented with the burden of also projecting the above other quality-related metrics, issues related to simulation speed and analysis accuracy get magnified by a large factor. Multi- and many-core modeling extensions exacerbate the problems even more. Furthermore: performance, power, temperature, and reliability are very much intertwined, complicating the process even further – when it comes to providing adequate support to analyze co-optimization and trade-off analysis. We will examine the techniques to model the benefits (and performance degradations) derived from on-chip power, temperature, and reliability management devices within the framework of current generation multi-core integrated models. We will discuss methods of validating pre-silicon integrated models and present real data to illustrate the errors that can result from inadequate high-level abstractions during early-stage modeling. We will cover academic research concepts that have benefited or influenced industrial practice in all aspects of the above problems, and we will point to open research issues and problems that need to be solved – especially in the context of technological changes brought forth by 3D chip integration

ORGANIZERS: Pradip Bose (IBM), Eren Kursun (IBM), Yuan Xie (Penn State)

KEYNOTE SPEAKER: Joel Emer (Intel)

TOPICS:

1. A review of processor-core and chip function, performance, power and temperature modeling methodologies during various stages of design.

2. Model validation and verification methodologies

3. Early-stage modeling techniques to determine lifetime reliability

4. A review of microarchitecture and system-level modeling techniques to predict soft error reliability

5. Multi-core power and inductive noise management: algorithms and evaluation.

6. Operating system and hypervisor effects and usage in system performance, power and reliability management.

7. Integrated co-optimization models (performance, power, temperature, reliability…).

8. Three-dimensional integration technology for multi-core architecture.

9. Open-mic Q&A + discussion session involving audience and speakers.