Tutorial: Integrated Multi-core Modeling

42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)

Westin New York at Times Square, New York City,

1:30 PM to 5:45 PM, December 13(Sunday), 2009

Pre-silicon function and performance modeling in the 21st century has quickly evolved, out of technology-driven necessity, into an integrated modeling art or science. No longer is it meaningful for architects to study performance (IPC) sensitivities in isolation, while product quality metrics like power, temperature and reliability are modeled only in late-stage design. With cycle-accurate performance models augmented with the burden of also projecting the above other quality-related metrics, issues related to simulation speed and analysis accuracy get magnified by a large factor. Multi- and many-core modeling extensions exacerbate the problems even more. Furthermore, performance, power, temperature, and reliability are very much intertwined, complicating the process even further when it comes to providing adequate support to analyze co-optimization and trade-off analysis. We will examine the techniques to model the benefits (and performance degradations) derived from on-chip power, temperature, and reliability management devices within the framework of current generation multi-core integrated models. We will discuss methods of validating pre-silicon integrated models and present real data to illustrate the errors that can result from inadequate high-level abstractions during early-stage modeling. We will cover academic research concepts that have benefited or influenced industrial practice in all aspects of the above problems, and we will point to open research issues and problems that need to be solved, especially in the context of technological changes brought forth by 3D chip integration

ORGANIZERS: Pradip Bose (IBM), Eren Kursun (IBM), Yuan Xie (Penn State)

KEYNOTE: Joel Emer, Intel

Joel S. Emer is an Intel Fellow, Digital Enterprise Group, and Director of Microarchitecture Research. Emer joined Intel as part of a June 2001 agreement with Compaq Computer Corporation that called for the transfer of microprocessor engineering and design expertise to Intel. Prior to joining Intel, Emer was a Compaq Fellow and Director of Alpha Architecture Research, where he led research efforts for future processors for Compaq's 64-bit family of servers. With over 25 years of combined service to Compaq and Digital Equipment Corporation, Emer has held various research and advanced development positions investigating processor microarchitecture designs and developing performance modeling and evaluation techniques. Emer is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology. He holds 15 patents and has published more than 30 papers. Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. Emer earned a doctorate in electrical engineering from the University of Illinois in 1979.

AGENDA:

Time	Topic	Speakers
1:30-2:20	KEYNOTE: Performance Analysis and Optimization for Multi-core Architecture	Joel Emer
2:20-3:50	Power/thermal: Modeling and Analysis for Multi-core Architecture	Pradip Bose Hans Jacobson David Brooks
3:50-4:00	Break
4:00-4:45	Reliability Modeling and Optimization for Multi-core Architecture	Mike Powell
4:45-5:45	Multi-core Architectures and Modeling in 3D	Eren Kursun Yuan Xie
5:45-6:00	Conclusion and Discussion

SPEAKERS BIOGRAPHY:

Pradip Bose is a Research Staff Member and Manager of the Reliability- and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center at Yorktown Heights, NY. He has been with IBM Research for over 25 years and has been involved in the architecture definition and associated pre-silicon modeling of the full range of IBM POWER-series microprocessors, beginning with the pioneering RISC super scalar research project in the early eighties. Pradip has a Ph.D from University of Illinois at Urbana-Champaign and is the author or co-author of over 80 peer-reviewed publications and is currently at the 12th invention achievement plateau level within IBM for his patent-related contributions. He has been actively involved in various IEEE/ACM conference committees and is the past editor-in-chief of IEEE Micro. He has given numerous past tutorials at conferences: ISCA, MICRO, HPCA, Sigmetrics, ICS, VLSI Design, VLSI Test Symposium, International Test Conference, etc. He is a Fellow of IEEE.

David Brooks joined Harvard University in September of 2002 and is currently a Gordon McKay Professor of Computer Science. Dr. Brooks received his B.S. (1997) degree from the University of Southern California and his M.A. (1999) and Ph.D (2001) degrees from Princeton University, all in Electrical Engineering. Prior to joining Harvard University, Dr. Brooks was a Research Staff Member at the IBM T.J. Watson Research Center. Dr. Brooks received an IBM Faculty Partnership Award in 2004, an NSF CAREER award in 2005, and a DARPA Young Faculty Award in 2007. His research interests include architecture and software approaches to address power, reliability, and variability issues for embedded and high-performance computer systems.

Hans M. Jacobson received an M.S. in Computer Science from University of Lulea, Sweden, in 1996 and a Ph.D. in Computer Science from University of Utah, USA, in 2004. Dr. Jacobson has been with IBM Research since 2001 where he has been involved in the development of several microprocessor test-chips and products. His main research focus has been in the area of microarchitecture power modeling and advanced low power techniques.

Eren Kursun is a Research Staff Member at IBM Research T.J. Watson Center, where she has been involved in research projects and test-sites focusing on power/temperature management and technology-aware design for microprocessor architectures. Dr. Kursun has published on energy-efficient and technology-aware microprocessor design; she received the best paper award in IEEE International Conference on Computer Design and IEEE Micro Top Picks. Dr. Kursun received her B.Sc. degree in Electrical and Electronics Engineering from Bogazici University; M.Sc. and Ph.D. degrees in Computer Science from the University of California, Los Angeles.

Mike D. Powell joined the Fault Aware Computing Technology (FACT) group at Intel Massachusetts in 2005. His research focuses on using computer architecture to manage the effects of technology scaling on high-performance microprocessors with emphasis on reliability and power. Before joining Intel, he completed his Ph.D at Purdue University under the supervision of Professor T. N. Vijaykumar.

Yuan Xie is an Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. He received Ph.D. degrees in electrical engineering from Princeton University. Before joining Penn State in Fall 2003, he was with IBM Microelectronic Division. He wasa recipient of the NSF CAREER award in 2006, and IBM Faculty Award in 2008. His research topics includes VLSI design, computer architecture, design automation, and embedded system designs. He is currently Associate Editor for IEEE Transaction on VLSI and IET Computers and Digital Techniques. He is also a co-editor for the book titled "Three Dimensional Integrated Circuit Design: Eda, Design and Microarchitectures" published in 2009.