Workshop on 3D Integration and
Interconnect-Centric Architectures
International
Symposium on High-Performance Computer Architecture 2009 (HPCA-15)
[Final Program]
Raleigh, North Carolina, Feb 15, 2009
http://www.cse.psu.edu/~yuanxie/HPCA-3d-workshop.html
On-chip interconnect has become a
significant determinant for the overall performance and power behavior of high
performance computer architecture in deep submicron designs. Various technology
and design solution alternatives are being actively explored to address the
interconnectivity problem including the use of: Three-dimensional Integrated
Circuits (3D-IC), RF and optical interconnect, as well as packet-based on chip
communication networks (Network-on-Chip). Among the proposed solutions,
three-dimensional integration has attracted significant attention in recent
years due to the improved interconnect characteristics that it enables. To
efficiently exploit the benefits of these technologies, design techniques and
methodologies are imperative; design space exploration at the architectural
level is also essential to fully take advantage of these technologies to build
high performance computer architectures. One of the main objectives of the
workshop is to provide a forum to explore cross-disciplinary issues in
interconnect-centric and stacked microprocessor design for future high performance
computer architectures, as well as encouraging discussion on the latest ideas
in the field.
Program Co-Chairs
-
Eren Kursun, IBM Research (ekursun@us.ibm.com)
-
Yuan Xie, Penn State
University (yuanxie@cse.psu.edu)
Technical Program Committee
- Rajeev Balasubramonian, University of Utah
- Keren
Bergmen, Columbia University
- Pradip
Bose, IBM
- Doug Burger, Microsoft
Research
- Jason Cong, University of California
Los Angeles
- Tom Conte, Georgia Institute
of Technology
- Chita
Das, NSF and Penn
State University
- Philip Emma,
IBM
- Norman Jouppi,
Hewlett-Packard
- Jian
Li, IBM Austin Research Labs
- Hsien-Hsin
Lee, Georgia Institute of Technology
- Gabe Loh,
Georgia Institute of Technology
- Pol
Marchal, IMEC
- Jaime Moreno, IBM
- Trevor Mudge,
University of Michigan
- Li-Shiuan
Peh, Princeton
University
- Tanay
Tarnik, Intel
- Glenn Reinman, University of California
Los Angeles
- Li Shang, Corolado University
- Xavier Vera, Intel Barcelona
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8:00-8:30
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Breakfast and Registration
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8:30-8:40
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Opening Remarks: Yuan Xie
(Penn State) and Eren Kursun (IBM Research)
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Session 1: Invited Talks
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8:40-9:20
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System Implications
of Integrated Photonics
Norm Jouppi, (Hewlett-Packard)
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9:20-10:00
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Memory Rich
Application Exploration for 3D Integration
Paul Franzon, (North Carolina State
University)
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10:00-10:30
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Coffee Break and Networking
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Session 2: 3D Memory
Architecture
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10:30-10:55
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Multi-Core Computer
Memory Hierarchy Design using Heterogeneous 3D Stacked DRAM
Hongbin Sun,
Jibang Liu, Nanning
Zheng, James Luy, Ken Rosey, and Tong Zhang
(Xian Jiaotong University and Rensselaer Polytechnic
Institute)
|
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10:55-11:20
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Power and
Performance Evaluation for 3D hybrid cache with Non-volatile memory
Xiaoxia Wu, Jian
Li, Lixin Zhang. Evan Speight, Yuan Xie, (IBM ARL and Penn State)
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11:20-11:45
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Interconnect and
Memory Tradeoffs in a Distributed FFT Processor Architecture for Synthetic
Aperture Radar in 2D-IC and 3D-IC
Thorlindur Thorolfsson,
Kiran Gonsalves, Paul Franzon
(North Carolina
State University)
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11:45-1:00
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Lunch
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Session 3: Invited Talks
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1:00-1:40
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Architecture
Implications of 3D Integration and Other Technologies
Dr. Philip Emma, (IBM Research)
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1:40-2:50
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Panel Discussion: Is 3D really a viable next step?
Prof. Yale Patt, Dr. Norman Jouppi, Dr.
Philip Emma,
Prof. Paul Franzon,
Prof. Hsien-Hsin Lee
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2:50-3:15
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Coffee Break and
Networking
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Session 4: 3D ICs
and Network-on-chip Architectures
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3:15-3:40
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Variation Aware
Routing for Three-Dimensional FPGAs
Chen Dong, Scott Chilstedt, and Deming
Chen, (UIUC)
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3:40-4:05
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3D IO interface
design between memory and Logic Dies on TSV interconnects
Marco Facchini, Paul Marchal,
Wim Dehaene, (IMEC and Katholieke University Leuven)
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4:05-4:30
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Save Your Energy: A
Fast and Accurate Approach to NoC Power Estimation
Christopher Mineo and W. Rhett Davis, (North Carolina State University)
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4:30-4:55
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Comparative Analysis
of Worst-Case Communication Delay Bounds for 2D and 3D NoCs
Yue Qian, Zhonghai Lu, and Wenhua Dou, (National
Univ. of Defense Technology in China and KTH in Sweden)
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Invited Talk: System Implications of Integrated
Photonics
Norm Jouppi, Director of
the Exascale Computing Lab, HP Lab
Norman P. Jouppi
received his Ph.D. in electrical engineering from Stanford
University in 1984, and a master of
science in electrical engineering from Northwestern University
in 1980. He is a fellow and director of the Exascale
Computing Lab at HP Labs, the company's central research and development arm,
overseeing research on building next-generation hardware and software compute
infrastructure using a cross-layer inter-disciplinary approach. Jouppi joined
HP in 2002 from Compaq Computer Corp., where he was a staff fellow at Compaq'
Western Research Laboratory in Palo
Alto, Calif. From
1984 through 1996, he was a consulting assistant/associate professor in the
department of electrical engineering at Stanford University,
where he taught classes in VLSI, circuits and computer architecture. He
currently serves as past chair of ACM Special Interest Group on Computer
Architecture (SIGARCH), is on the ACM Council and on the Computing Research
Association (CRA) board. He is on the editorial board of Communications of the
ACM and IEEE Computer Architecture Letters, and is a fellow of the ACM and the
IEEE. He holds more than 35 U.S.
patents. He has published over 100 technical papers, with several best paper
awards and one International Symposium on Computer Architecture (ISCA)
Influential Paper Award.
Invited Talk:
Architecture Implications of 3D Integration and Other Technologies
Philip Emma, Master
Inventor/Manager of Technology and Microarchitecture Group, IBM Research
Philip Emma received
B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Illinois,
joining the IBM T. J. Watson Research
Center in 1983. Since
then, he has done extensive work in the areas of computer microarchitecture,
computer architecture, systems design, circuit design, electronic packaging,
materials, interconnection technology, and optics. He led the definition and
design of the R-unit on the first IBM CMOS processors for IBM zSeries* machines and was responsible for the reliability
and infrastructure that makes the zSeries machines
the premier brand for reliable computing in the industry. Dr. Emma has written
more than 200 technical articles and several book chapters, he holds 35
Invention Plateaus and more than 100 patents, and he has received several
corporate awards for his technical work. He is an IBM Master Inventor, a member
of the IBM Academy of Technology, and a Fellow of the Institute of Electrical
and Electronics Engineers. He is currently Manager of the IBM Systems
Technology and Microarchitecture Group.
Panelist: Yale Patt, Professor, University of Texas Austin
Yale Patt is a teacher
at The University of Texas at Austin,
where he also directs the research of nine PhD students, while enjoying an
active consulting practice with several microprocessor manufacturers. He
teaches the required freshman intro to computing course to 400 first year
students every other fall, and the advanced graduate
course to PhD students in microrchitecture every
other spring. His research ideas (HPS, branch prediction, etc.) have been
adopted by almost every microprocessor manufacturer on practically every high
end chip design of the past ten years. Yale Patt has earned the appropriate
degrees from reputable universities and has received more than his share of
prestigious awards for his research and teaching. More detail on his interests
and accomplishments can be obtained from his web site: www.ece.utexas.edu/~patt
Invited Talk:
Memory Rich Application Exploration for 3D Integration
Paul Franzon, Professor, North Carolina State
University
Paul D. Franzon earned his Ph.D. from the University
of Adelaide, Adelaide, Australia
in 1988. He has worked at AT&T Bell
Laboratories, DSTO Australia, Australia Telecom and two companies he
cofounded, Communica and LightSpin
Technologies. His current interests center on the technology and design of
complex systems incorporating VLSI, MEMS, advanced packaging and molecular
electronics. Application areas currently being explored include novel advanced
packaging structures, Network Processors, SOI baseband radio circuit design for
deep space, on-chip inductor and inductance issues, RF MEMS, and moleware circuits and characterization. He has lead
several major efforts and published over 120 papers in these areas. In
1993 he received an NSF Young Investigators Award, in 2001 was selected to join
the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished
Alumni Professor, and in 2005 won the Alcoa award. He
is a Fellow of the IEEE.
Panelist: Professor Hsien-Hsin
Sean Lee, Georgia Institute of Technology
Hsien-Hsin S. Lee received his BSEE from National Tsinghua
University, and his MSE and PhD from
the University of Michigan at Ann
Arbor. He is an Associate Professor of the School of Electrical
and Computer Engineering at Georgia Tech and serving the first Associate
Director of the new Center
of Manycore Computing
at Georgia Tech. His current research interests include computer architecture,
3D Integrated Circuits, low-power VLSI, and information security. Prior to
joining academia, he was a processor architect at Intel Corporation and later
the architecture manager of StarCore DSP Technology
Center of Agere systems and Motorola. Dr. Lee's
doctoral thesis was awarded the Horace H. Rackham School Distinguished
Dissertation Award at the University of Michigan and has co-authored three
papers that won the Best Paper Awards at MICRO-33, CASES-04, and IBM PAC^2. Dr.
Lee received a DOE Early CAREER PI Award, NSF CAREER Award, and Georgia Tech's
ECE Outstanding Jr. Faculty Member Award. He holds 4 U.S. patents
.