Speaker Biography:

Juan-Antonio Carballo has been a semiconductor and nanotechnology partner at IBM's Venture Capital Group since 2004, and currently heads IBM's Microelectronics Services business worldwide. He has worked and studied in three continents. In 2007, Dr. Carballo was on leave as a partner of Argon Venture Partners, the first VC firm focused on synergies between the US and Canada. In 2006, Juan-Antonio was on assignment in China to bootstrap IBM's VC presence and ecosystem. In 2004 and 2005, Juan-Antonio established first-time partnership initiatives around IBM hardware architectures, bringing in hundreds of new VC and start-up relationships or deals, spearheading the first $100m platform fund initiative with Walden International around blades, and creating the first VC board around an open Power processor platform. For this work, he was named number one "Top 40 Under 40" by American Venture Magazine in 2006. Prior to his work IBM's VC Group, Juan-Antonio led research in adaptive communications chips and systems at IBM Research. He won several IBM awards for driving work in this area. He filed over 25 patents and has around 50 publications in semiconductors, systems, energy-efficient design, engineering economics, and collaboration software. He has written a book available worldwide, called "Chip Design for Non-Designers: An Introduction". He has been Chair of the International Design Technology Roadmap for Semiconductors, the 2004-5 CTO VSIA IP standards organization, the Chair of the IEEE Committee on Electronic Design Automation, Executive Committee member of IEEE ICCAD, advisor to several top start-ups, and organizer of dozens of conferences. His prior work experience includes stays at Digital Equipment, LSI Corp., Accenture, and EDF. Juan-Antonio holds a Ph.D. in Electrical and Computer Engineering from the University of Michigan, an M.B.A. from the College des Ingenieurs (Paris), and a M.Sc. in Telecommunications Engineering from the Universidad Politecnica de Madrid.

Ramesh Chandra is Sr Staff Manager at Qualcomm's QCT division (ASIC division) and working on SoC Verification at San Diego. His areas of interest areas include SoC/Architecture modeling and verification, HAL (Hardware abstraction layer aka HdS) based verification and simulation acceleration. He received B.E. (Electrical and Electronics) and M.Sc. (Mathematics) from Birla Institute of Technology and Science, Pilani, India.

Mary Jane Irwin received the M.S. (1975) and Ph.D. (1977) degrees in computer science from The University of Illinois, Urbana-Champaign. Dr. Irwin has been on the faculty at Penn State since 1977. She received an Honorary Doctorate from Chalmers University, Sweden, in 1997 and the Penn State Engineering Society's Premier Research Award in 2001. She was awarded the ACM Distinguished Service Award and the CRA Distinguished Service Award, both in 2006. Dr. Irwin was named a Fellow of IEEE in 1995, a Fellow of ACM in 1996, was elected to the National Academy of Engineering in 2003, and was elected to the American Academy of Arts and Science in 2009. She was named the A. Robert Noll chair of Engineering in 2003 and a Penn State Evan Pugh Professor in 2006.

Jan M. Rabaey received the EE and Ph.D degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium, respectively in 1978 and 1983. From 1983 till 1985, he was connected to the University of California, Berkeley as a Visiting Research Engineer. From 1985 till 1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he holds the Donald O. Pederson Distinguished Professorship. He has been a visiting professor at the University of Pavia (Italy) and Waseda University (Japan). From 1999 till 2002, he served as associate chair of the EECS Dept. at Berkeley, Currently, he is director of the Gigascale Research Center (GSRC), and the scientific co-director of the Berkeley Wireless Research Center (BWRC).Jan Rabaey authored or co-authored a wide range of papers and books in the area of signal processing, digital architectures and circuits, and design automation. He is the author of the popular "Digital Integrated Circuits -- A Design Perspective" textbook. He received numerous scientific awards, including the 1985 IEEE Transactions on Computer Aided Design Best Paper Award (Circuits and Systems Society), the 1989 Presidential Young Investigator award, the 1994 Signal Processing Society Senior Award, and the ISSCC 2002 Jack Raper Outstanding paper award for Technical Directions. He is an IEEE Fellow, is past chair of the VLSI Signal Processing Technical Committee of the Signal Processing Society and is serving on the executive committee of the Design Automation Conference in the function of past Chair. He chaired the International Symposium on Low Power Electronics and the IFIP Conference on Mobile Computing in 1996. In 2008, he received the IEEE CAS Mac Van Valkenburg Award.His current research interests include the conception and implementation of next-generation integrated wireless systems. This includes the analysis and optimization of communication algorithms and networking protocols, the study of low-energy implementation architectures and circuits, and the supporting design automation environments.

Andres Takach is a Chief Scientist at Mentor Graphics. He joined Mentor Graphics in 1997, where he has worked on all aspects of high-level synthesis. His fields of interest are in high-level synthesis, synthesis for low-power, embedded system design, and hardware/software codesign. From 1993 to 1997, he was a faculty member at Illinois Institute of Technology, where he conducted research in high-level synthesis and hardware/software codesign. Andres Takach received his Ph.D. degree from Princeton University in 1993 and his B.S. and M.S. degrees in electrical and computer engineering from the University of Wisconsin-Madison in 1986 and 1988, respectively.