A three dimensional (3D) chip is a stack of multiple device layers with direct vertical interconnects tunneling through them. A key benefit of this approach over a traditional two dimensional chip is the ability to reduce the length of long interconnects. Prior efforts have focused on developing different fabrication techniques involved in stacking multiple device layers and in forming the vertical interconnects. The size and density of the vertical interconnects that can tunnel between the different device layers varies based on the underlying technology used to fabricate the 3D chips.  To efficiently exploit the benefits of 3D technologies, design techniques and methodologies for supporting 3D designs are imperative.

Our 3D IC research projects were supported by NSF, SRC, DOE, DARPA, IBM, Qualcomm, and ITRI, with 3D chip fabrication supported by MITLL, Tezzaron, and IMEC.

New: The book "Three-dimensional IC: Design, CAD, and Architecture" edited by Yuan Xie, Jason Cong, Sachin Sapatnekar is published by Springer.

Tool Release:

Selected Publications:

Tutorial:   

Invited Talks on 3D IC:

02/2009 Semiconductor Research Corporations (SRC) . Raleigh, NC
  " 3D IC Design and Architecture"  
02/2009 Duke University. Durham, NC
  " 3D IC Design and Architecture"  
09/2008 Univ. of Texas in Austin. Austin, TX
  " 3D EDA and Architecture"  
09/2008 IBM Austin Research Labs. Austin, TX
  " 3D EDA and Architecture"  
09/2008 Freescale. Austin, TX
  " 3D EDA and Architecture"  
11/2007 Qualcomm. San Diego, CA
  " 3D EDA and Architecture"  
10/2007 Seagate Technology LLC. Bloomington, MN
  " 3D IC Design Tutorial"  
10/2007 SEMATECH 3D workshop Albany, New York
  "3D Archtecture Design"  
09/2007 KAIST University Daejeon, Korea
  "Design Space Explorations for 3D ICs"  
05/2007 Honda Research Institute. Tokyo, Japan
  "Design Automation for Three-dimensional ICs"  
05/2007 Peking University Beijing, China
  "New Dimension for High Performance"  
04/2007 IMEC (Interuniversity Microelectronics Centre) Leuven, Belgium
  "The Challenges of Designing 3D Microarchitectures"  
01/2007 Dagstuhl Seminar on Power-Aware Computing Systems. Dagstuhl, Germany
  "Thermal Challenges in 3D Microarchitecture Design"  
11/2006 The 3rd Annual 3D Architecture Conference. San Francisco, CA
  "Design Space Exploration for 3D IC Design;  
10/2006 University of Pittsburgh. Pittsburgh, PA
  "The Challenges of Designing 3D Microarchitectures"  
08/2006 Hongkong University of Science and Technology Hong Kong, China
  "3D Microarchitecture Design"  
08/2006 Intel China Research Center Beijing, China
  "3D Microarchitecture Design"  
03/2006 IBM T.J.Watson Research Center. Yorktown, NY
  "The Challenges of Designing 3D Microarchitectures"