Short Bio: Prof. Xie received his B.S. degree from Tsinghua University, and his M.S. and Ph.D. degrees from Electrical Engineering Department, Princeton University. Prior to joining Penn State in Fall 2003, he worked as an Advisory Engineer for IBM Microelectronics Division's Worldwide Design Center. He was a recipient of the NSF CAREER award. For more information, please click here for the curriculum vitae.
Research Interests : VLSI Design, Electronics Design Automation, Computer Architecture, Embedded Systems Design.
--- Congratulations for 4 papers accepted by DAC 2014.
--- New book Emerging Memory Technologies: Design, Architecture, and Applications is published by Springer.
--- Jishen Zhao's paper Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support received the Best Paper Honorable Mention Award at MICRO-46.
--- ISLPED 2014 will be held in San Diego. Dr. Xie serves as the General co-chair.
--- ISLPED 2013 was held in Beijing on Sept.4-6, 2013. Dr. Xie serves as the TPC co-chair.
--- ASPDAC 2013 was held in Yokohama, Japan. Dr. Xie served as the TPC chair.
--- Guangyu Sun received 2012 EDAA Outstanding Dissertation Award .
--- Best paper award at ISVLSI 2012 .
--- Best paper award at ISLPED 2011 .
--- Xiangyu Dong named ACM Student Research Contest winner and awarded at the ACM Awards Banquet on June 4, 2011.
--- More news....
Recent Chip Tapeout:
--- Two 3D chips taped out in 2009 by MITLL with 180nm and 3-layer stacking are back in 2010/9.
--- One chip taped out by MITLL with 130nm subthreshold SOI technology in 2010/7.
--- One 3D chip tapeout with IMEC at 32nm in 2010/7.
--- Two 3D chips taped out by Tezzaron and Globlefoundries in 130nm in 2010/3.
Selected Research Projects: (Click here for more details about his research)
--- [3DIC: EDA,Architecture and Application for Emerging 3D ICs]
--- [MAAEMO: Modeling, Architecture and Application for Emerging Memory Technologies]
--- [Variation Aware Design Methdologies]
--- [Soft Errors Analysis and Mitigation]
--- [Low Power and Thermal-Aware Design]
--- [Embedded System Synthesis/Design]
University Park, PA, 16802
Email: yuanxie AT cse dot psu dot edu