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Gem5+DRAMsim2 Integration Patch
Gem5 and DRAMsim2 are two great tools for memory architecture researchers like me. Unfortunately, DRAMsim2 has not been ported to Gem5 so far. Therefore, I decided to integrate them myself.
I tried to make minimal changes to the source codes of both tools. In the patch, the obsolete DRAMMemory class in Gem5 will be replaced by a simple port to DRAMsim2. Here, I provide the patch files.
Gem5 patch: This patch is generated on the basis of Gem5 development repository (revision 8643). There is NO need to download DRAMsim2. The patch will automatically import all the necessary DRAMsim2 source codes.
Sample run: ./build/ARM_SE/m5.opt configs/example/se_dramsim2.py -t
DRAMsim2 patch: This patch only shows the changes made on the DARMsim2 side. The baseline DRAMsim2 code is the one committed on Dec 15, 2011.
Gem5 and DRAMsim2 are two great tools for memory architecture researchers like me. Unfortunately, DRAMsim2 has not been ported to Gem5 so far. Therefore, I decided to integrate them myself.
I tried to make minimal changes to the source codes of both tools. In the patch, the obsolete DRAMMemory class in Gem5 will be replaced by a simple port to DRAMsim2. Here, I provide the patch files.
Gem5 patch: This patch is generated on the basis of Gem5 development repository (revision 8643). There is NO need to download DRAMsim2. The patch will automatically import all the necessary DRAMsim2 source codes.
Sample run: ./build/ARM_SE/m5.opt configs/example/se_dramsim2.py -t
DRAMsim2 patch: This patch only shows the changes made on the DARMsim2 side. The baseline DRAMsim2 code is the one committed on Dec 15, 2011.
NVSim
NVSim is a generalized extension of PCRAMsim. NVSim not only includess the performance, energy, and area models of phase-change memory, it also adds the support for spin-torque-transfer memory (STT-RAM), memristor-based resistive memory (R-RAM), and conventional NAND flash.
NVSim uses the same modeling principles as the well-known CACTI tools, but it starts from scratch on the basis of a brand-new framework with more flexibility. Like CACTI, NVSim also has the capability of modeling SRAM/DRAM/eDRAM as either cache or memory.
We just set up a wiki site that describes more details including the download source.
NVSim is a generalized extension of PCRAMsim. NVSim not only includess the performance, energy, and area models of phase-change memory, it also adds the support for spin-torque-transfer memory (STT-RAM), memristor-based resistive memory (R-RAM), and conventional NAND flash.
NVSim uses the same modeling principles as the well-known CACTI tools, but it starts from scratch on the basis of a brand-new framework with more flexibility. Like CACTI, NVSim also has the capability of modeling SRAM/DRAM/eDRAM as either cache or memory.
We just set up a wiki site that describes more details including the download source.
PCRAMsim
Phase-change random access memory (PCRAM) is an emerging memory technology with attractive features, such as fast read access, high density, and non-volatility.
To enable the system-level design space exploration of PCRAM, PCRAMsim is developed to model PCRAM performance, energy, and area and is validated against industrial PCRAM prototypes.
The technical details are available in my ICCAD2009 paper. The development of this tool is now a part of NVSim. Please kindly cite this paper if this tool is helpful to your research.
Phase-change random access memory (PCRAM) is an emerging memory technology with attractive features, such as fast read access, high density, and non-volatility.
To enable the system-level design space exploration of PCRAM, PCRAMsim is developed to model PCRAM performance, energy, and area and is validated against industrial PCRAM prototypes.
The technical details are available in my ICCAD2009 paper. The development of this tool is now a part of NVSim. Please kindly cite this paper if this tool is helpful to your research.
A Web-Based 3D IC Cost Model
When 3D IC becomes a hot topic in chip fabrication, people may ask such a question like, how much a 3D chip will be? As a part of my ASPDAC2009 paper, I tried to establish a cost model to answer that question.
Unfortunately, due to some intellectual property issue, I cannot publish the source code. Instead, I setup this web-based interface for people who are interested in it.
[Link]
When 3D IC becomes a hot topic in chip fabrication, people may ask such a question like, how much a 3D chip will be? As a part of my ASPDAC2009 paper, I tried to establish a cost model to answer that question.
Unfortunately, due to some intellectual property issue, I cannot publish the source code. Instead, I setup this web-based interface for people who are interested in it.
[Link]
Linux Kernel Hacking: signal-per-fd
signal-per-fd is a modification to the realtime signal handling approach which reduces or eliminiates realtime signal queue overflow by enforcing each socket can only have one signal at a single time.
This approach is proposed by two HP researchers, Chandra and Mosberger, in their paper Scalability of Linux Event-Dispatch Mechanisms.
I implemented this feature on Linux Kernel 2.6.27. (I'm quite excited because this is my first time to hack an OS kernel.) The signal-per-fd function can be enabled by the code:
fcntl(sock, F_SETAUXFL, O_ONESIGFD);
where sock is the file descriptor that needs the feature.
[Download]
signal-per-fd is a modification to the realtime signal handling approach which reduces or eliminiates realtime signal queue overflow by enforcing each socket can only have one signal at a single time.
This approach is proposed by two HP researchers, Chandra and Mosberger, in their paper Scalability of Linux Event-Dispatch Mechanisms.
I implemented this feature on Linux Kernel 2.6.27. (I'm quite excited because this is my first time to hack an OS kernel.) The signal-per-fd function can be enabled by the code:
fcntl(sock, F_SETAUXFL, O_ONESIGFD);
where sock is the file descriptor that needs the feature.
[Download]
LaTeX Table Transposer
Once I revised one of my one-column paper drafts to be a two-colum final version using LaTeX, I found I had to transpose lots of 'fat but short' tables into 'slim but long' ones to fit the paper layout. Some of those tables were full of tons of experimental data, and it was really tedious to transpose them manually. That's why I wrote this little program. Hope it would be useful to someone who faces the same problem.
[Download]
Command: latextt
Input example: [here]
Output example: [here]
Once I revised one of my one-column paper drafts to be a two-colum final version using LaTeX, I found I had to transpose lots of 'fat but short' tables into 'slim but long' ones to fit the paper layout. Some of those tables were full of tons of experimental data, and it was really tedious to transpose them manually. That's why I wrote this little program. Hope it would be useful to someone who faces the same problem.
[Download]
Command: latextt
Input example: [here]
Output example: [here]