Note: Most of these questions are gathered through the expertise of many groups using the Micromagic tools. 1. Postscript printing problems with Max There have been a number of questions today about the postscript printing from MAX. We didn't have any customers using this option, so it was taken out. We just forgot to take it out of the menu. We are adding in an interface to Hyperplot which has a postscript printing option. Solution: Use xv or xgrabsc tools to capture the image from the screen. 2. Sue simulation results from HSPICE seem to be faulty. The HSPICE files are dummy files. You will need to change the ./mmi_990910/mmi_local.sample/sue/default_spice_header.h to include 0.25u HSPICE model file that can be obtained from the MOSIS web site (http://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/tsmc-025/n94s-params.txt) 3. When I go to extract the netlist, I get lots of subcells with names like: #fet!-type!pfet!-contacts!left!-width!1.2 In the local menu, there should be an "extract it" command. If so, use this command. What it does is first flatten all of the gcells (fets and vias) and then extracts the .ext file which can now be used for ext2sim and ext2spice. -------------------------- The following lines should be in $MMI_TOOLS/../mmi_local/max/.maxrc # Add the lvs_it command source $MMI_LOCAL/max/lvs_it.tcl menu_local_cmd "lvs it" lvs_it # Add the extract_it command to extract .ext files menu_local_cmd "extract it" extract_it # Needed so that highlite/select works properly set LAY_STIPPLE_SELECTION 1 # puts the layout generator in the tool menu menu_tool_cmd "Layout Generator" stdcell_load_sim --------------------- 4. Related to the layout generator. it seems it only wants to do a single row, and flattens any hierarchy that exists in the Sue files. The layout generator is an aid for doing layout. At a minimum, it puts the devices of the correct size in the layout with flylines to show connectivity. You can move the devices anywhere you what and the flylines will follow. It was initially designed for standard cell layout but you can use it for any type of layout by turning off the standard cell layers. Also, currently the crossprobing only cross probes nets, not devices. 5) In Sue, running irsim the "X" command on the menu does not "release" the node. It sets the node to be X which if true is not useful. The command one would want is the irsim command "x" (lowercase) which releases the node (taking it off the input list) so that simulation will change its value. The work-around is to go to the sue> window and type i x i means its a irsim command, x is the release command, is.. 6) In MAX the label command window has a choice for global signals. but it labels globals !node this is the opposite from the conventions we are all used to of node! for globals (esp Vdd! and GND! which ext2spice looks for). I do not know if any micromagic tools care about this, if not it would be good to change it. work around - call it local and type the ! yourself. GND! and Vdd! The ! at the front of a global label is not part of the text of the label. It does not get output in the .sim file. The types of labels (input, output, global, etc.) are only used by some of our newer tools (i.e. MegaCell Compiler). If you need GND! to be the label, then type in the name as "GND!". It doesn't matter if you define it as local or global as far as the netlist goes, but if you define it as a global you'll see !GND! on the schematic. 7) For cross probing (as far as we can tell) you MUST flatten the MAX file otherwise the cross probe can not match. Also it seems you must be mostly or completely wired up before you try to cross probe. you can undo the flatten before you do the final save. Flattening cells before crossprobing is needed for now. So, if you layout an AND using a NAND and INV cell, you need to flatten the AND before crossprobing. The gcells for fets and vias don't need to be flattened. We're looking into handling hierarchical crossprobing in a future release. 8) In SUE in the new library set there are some similar cells in both the "spice" library and the std cell set. In particular inverters and aoi. They are not the same. The spice ones are set up to be easy to resize, the std cell ones are not. (I guess that makes sense). If you use the spice cells it does not wire things up to Vdd and GND in the layout generator, if you use the std cells it does. 9) Both max and sue like to keep their "main/parent" window on top. sometimes when you are working with some sub-window popup, it gets lost behind the parent. - if you see a ? floating on the screen, that is what happend. look for the popup. 10) ext2spice has flags for -r0 -c0 to get all the resistance and capacitance values out of the ext files. If you bring up the MMI documentation (type "mmidoc" on the command line) and look at the ext2sim documentation you'll see "Extcheck Man Page". This documents the -r and -c options. 11) More notes on max circuit extraction some more notes on extraction: Some of my students are trying to flatten cells to help with the extraction problem. We note that flattening an array of cells deletes all but the original cell. When you load two cells into a new higher cell, if their bounding boxes overlap, then the extractor gets very confused. We have even seen Vdd and GND get shorted in the extraction file. (merge vdd gnd) What seems to work: a) in your leaf cells (nand/nor etc) flatten out the gcells (the fets) b) in your hierarchical cells abut the leaf cells, paint over the vdd and GND rails and add a new Vdd/Gnd label to the fresh paint. Also, if you want labels on the top level put new paint over the sub-cells and put down labels. (just like magic).