The Calculator LabsThis series of three labs was created by IBM for teaching internal functional verification classes. From a design standpoint, each of the labs builds upon the previous. From a verification standpoint, each lab requires more and more elaborate processes to verify. Each lab has "bugs" built into the design. These bugs have disable switches that fix the problem after the student has encountered the bug.Calc1 Design Description Calc1 VHDL ZIP Calc1 Verilog ZIP Calc1 is a simple four input, four function calculator. Calc2 Design Description Calc2 VHDL ZIP Calc2 Verilog ZIP Calc2 adds pipelining concepts to the first exercise. Calc3 Design Description Calc3 VHDL ZIP Calc3 Verilog ZIP Calc3 adds internal register data and new instructions, transforming the calculator into a processor. Calc1 bugs can be uncovered using handcoded, deterministic testcases. By leading off the class with a deterministic testcase lab, the students will learn the basics of debugging while getting a glimpse of the drawbacks of a deterministic-only verification strategy. This will also allow the students to become familiar with the simulation engine and its usage. A simple testcase to perform an add instruction (5 + 8) might look like this: Calc1 simple testcase. Calc3 bugs need to use an advanced, random based methodology to uncover. This lab may be done in teams, where random driving behaviorals, checking monitors, and automated results checking tasks must be shared by the team. Here is an example of the final environment, done in Verisity's Specman: Specman Calc3 (this is a zip file). Lab Mechanics - Provides an overview of lab management, duration, support. |