Current Students

 

  1.      Andrew Ricketts, Ph.D./CSE, Thermal-aware adaptive architectures
  2.  Ramakrishnan Krishnan, Ph.D./EE,  Reliability Effects of Soft Errors and NBTI on Digital Circuits (Co-advised with Dr. Datta)
  3. Niranjan Soundararjan, Ph.D./EE, Robust Computer Architecture (Co-advised with Dr. Sivasubramaniam)
  4.  Soumya Eachempati, Ph.D./CSE, FPGA Architectures in Emerging Technologies (co-advised with Dr. Yuan Xie)
  5. Prasanth Mangalagiri, Ph.D./CSE, Reconfigurable Supercomputing (co-advised with Dr. Xie)
  6. Sungmin Bae, Ph.D./CSE, Robust FPGA Architectures
  7.  Mike Debole, Ph.D./CSE, Aging-Aware Microarchitectures (co-advised with Dr. Xie)
  8. Melvin Eze, Ph.D./CSE, Reliable on-chip interconnect architectures (co-advised with Dr. Irwin) - Bunton Waller Fellow
  9. Srinidhi Kestur Srinidhi Kestur, Ph.D./EE, Automated Generation of Signal Processing Systems(Co-advised with Dr. Suman Datta)
  10. Ahmed Al Maashri, Ph.D./CSE, 3D Architectures – Govt of Oman Fellowship
  11. Vinay Saripalli, Ph.D./CSE, Ultra-Low Voltage Architectures (Co-advised with Dr. Suman Datta)
  12. Vikram Sampath Kumar, MS/EE, FPGA based accelerators
  13. Aditi Rathi, MS/EE, GPU accelerated Feature Recognition
  14. Jesse Scott, MS/CSE, FPGA based Image recognition

 

Visiting Scholars

 

  1.   Madhu Mutyam, Govt. of India BOYSCAST (Better Opportunities for Young Scientists in Chosen Areas of Science and Technology) Postdoctoral Scholar (2005-2006) (Currently Assistant Professor at IIT Madras)
  2.  Emanuele Lattanzi, visiting Ph.D. student, Univ. of Urbino, Italy (in 2003)  
  3.  Pablo Ituero, visiting Ph.D. student in 2007, (assistant professor - Universidad Politécnica de Madrid, Spain)


Former Students

Ph.D 

  1. Hyun Suk Kim, Energy-Aware Hardware and Software Optimizations, August 2004 (Samsung Electronics, Korea) (co-advised with Dr. Irwin)
  2.      Soontae Kim, High Performance and Low Power Cache Architectures, December 2003 (ICU, Korea )
  3.   Jie Hu, Architectural and Compiler Support for Energy Efficient Caches, August 2004 (NJIT)
  4. Lin Li, Designing Energy Efficient and Reliable Caches and Interconnects, August 2005 (Intel, Portland)(co-advised with Dr. Irwin)
  5.  Yuh-Fang Tsai, Ph.D./CSE Leakage Energy Modeling, August 2005 (Taiwan)
  6. See full size image Vijay Degalahal, Ph.D/CSE, Soft Errors; Modeling and Interactions with Power Optimizations, August 2005 (Intel, Bangalore)
  7. Hendra Saputra, Ph.D./CSE, Security issues in embedded systems, August 2005 (co-advised with Dr.Kandemir)(Institute of Information Research, Singapore)

 

  1.  Theo Theocharides , Ph.D/CSE, Application Specific Multiprocessor Systems on Chip, December 2005 (University of Cypress)
  2.  Jooheung Lee, Ph.D./EE, VLSI Architectures for Video Processing, August 2006 (co-advised with Dr. Jenkins, Electrical Engineering)(University of Central Florida)
  3. Greg Link, Ph.D./CSE,  Thermal Issues in Next Generation Microprocessors, August 2006 (CAC Fellow)(University of York)
  4. Aman Gayasen, Ph.D./CSE,  Power-Aware FPGAs, Dec 2006 (co-advised with Dr. Kandemir)(Achronix)
  5. Rajaraman Ramanarayanan, Ph.D./EE, Soft Errors in Logic and Memory Systems (co-advised with Dr. Jenkins, Electrical Engineering) (Intel, Bangalore)
  6. Matthew Pirretti, Ph.D./CSE, Secure Embedded and Mobile Systems (Motorola)
  7. Ing-Chao Lin, Ph.D./CSE, High-Level Power and Reliability Estimation (co-advised with Dr. Irwin) (NCKU, Taiwan)
  8. Suresh Srinivasan, Ph.D./CSE, Power-Aware Robust FPGA Systems (Intel, Bangalore)
  9. Chrysostomos Nicopoulus, Ph.D./EE, Architectural Innovations for for On Chip Networks (EPFL) (Co-advised with Dr. Jenkins) – 2008 EDAA Outstanding Dissertation Award
  10. Jung Sub Kim, Ph.D./EE, Algorithm-Architecture Co-Design for Signal Processing Systems (Samsung) (Co-advised with Dr. Jenkins)
  11. Kevin Irick, Ph.D./CSE, Smart Sensors (Postdoc – Penn State)

 

Masters

  1. Anupama Murthy, Memory System Characterization of Java Applications, May 2000 (at Helwett Packard, Bay Area)
  2. Rajendra Athavale, Annotation Based Energy Optimization for Java, December 2000 (at Dell, Austin)
  3. Tendai P. Chinoda, Protecting Java Applications Against Decompilation via Control Flow Obfuscation, December 2000 (At IBM, Pittsburgh)
  4. Samarjeet Tomar, Characterizing and Optimizing Memory Energy in Java, May 2001 (At Oracle, CA) (co-advised with Dr. Kandemir)
  5. Jeyran Hezavei, Power Modeling and Optimization of Memories and Functional Units , May 2001 (co-advised with Dr. Irwin)
  6. Gandhi Thirugnanam, Low Power Content Addressable Memory Design, May 2001 (at IBM)
  7. David Charles, Improving ILP with Instruction Reuse Cache Hierarchy, May 2001 (Co-advised with Dr. Hurson)
  8. Jun Zhao, Influence of MPEG-4 Parameters on System Energy, August 2001 (at Synospys, CA)
  9. Preeti Garg, Implementation of a Java Accelerator:  Interfacing the Java Virtual Machine with the FPGA, August 2001
  10. Nandagopal Kirubanandan, Memory Energy Characterization and Optimization of SPEC2000 Benchmarks, December 2001 (at Motorola) (co-advised with Dr. Sivasubramaniam)
  11. Geethanjali Esakkimuthu, Memory Energy: Modeling and Optimizations, December 2001 (At Unisys, PA)(co-advised with Dr. Irwin)
  12. Balaji Viswanathan, OS Paging Issues for DRAM Energy Management, December 2001 (Co-advised with Dr. Sivasubramaniam)
  13. Xiheng  Xu, Evaluating Energy-Efficiency of Channel Coders, May 2002 (co-advised with Dr. Irwin)
  14. Hendra Saputra, Compiler-directed Voltage Scaling for Reducing Energy, December 2001 (co-advised with Dr. Kandemir)
  15. Yuh-Fang Tsai, Characterization and Modeling for Run-time Leakage Reduction Techniques, December 2002 (co-advised with Dr. Irwin)
  16. Nachiket Shikhare, Leakage Power Estimation Tool for CMOS Circuits, May 2003 (with Cypress Semiconductors, India) (co-advised with Dr. Irwin)
  17. Ananth Hegde Ankadi, Variable Line Sized Cached DRAM, August 2003 (Software Consultant, NY)
  18. Grace Eberhardt, Analyzing the Common Language Runtime, August 2003 ((at SMG Inc.)(co-advised with Dr. Saraswat)
  19. Christopher Oster, A Workload Characterization and Performance Analysis of Multiprocessor Immersive Display Environments, December 2003 (at Lockheed Martin, Valley Forge)
  20. Eric Swankoski, Encryption and Security in SRAM FPGAs, May 2004 (at Naval Research Labs)
  21. Kiyoung Lee, Leakage control mechanism for FPGAs, August 2004
  22. Swapna Dontharaju, Soft error analysis of CAMs, August 2004 (Intel)
  23. Thomas Richardson, MS/CSE, On-Chip Interconnects, Dec 2005 (Availink, Inc.) (co-advised with Y. Xie)
  24. Kevin Irick, MS/CSE, Embedded Face Detection, May 2005 (Ph.D. Student at Penn State)
  25. Priya Sundararajan, MS/CSE, Mapping Signal Processing Applications on FPGAs, Dec 2006 (Availink, Inc.)
  26. Adil Sarwar, December 2006, M.S./CSE, Performance Evaluation of SystemC and Verilog for RTL Synthesis and System Modeling (Intel)
  27. Raghavan Ramadoss, December 2006, M.S./CSE, Static and Runtime Optimization Strategies for Variation Aware MPSoC Platforms (Cisco)
  28. Charles Addo-Quaye, May 2007, M.S./CSE, Thermal-Aware Placement and Variation for Three Dimensional Network-on-Chip Designs (Co-advised with Prof. Xie) (Ph.D. Student at PSU)
  29. Han-Wei Chen, August 2007, M.S./CSE, Impact of Circuit Degradation on Design Security of Field programmable Devices (Co-advised with Prof. Xie) (Law Student at UT Austin)
  30. Srinath Sridharan, May 2008, M.S./CSE, Performance-Reliability Tradeoffs in designing reorder buffers (Ph.D. student at U.Wisconsin)
  31. Amol Mupid, Dec 2008, M.S./CSE, Variation-aware CAM structures
  32. Kate Kilroy, Dec 2008, M.S./CSE, A Signal Based Approach to an Instrument Driver System (Lockheed Martin)
  33. Srijith Rajmohan, MS/EE, Parallel Image processing (Ph.D. Student at U. Tennessee)

Undergraduate Honors Thesis

  1. Victor Lyuboslavasky, Charge Recovery Buses, May 2000 (at AMD, Austin)
  2. Brandon Rioja, Performance Tradeoffs in Client Server Partitioning of Java Applications, May 2003
  3. Lan Vuong, Dynamic Web Design for Multiple Platforms, May 2003 (with IBM, Research Triangle)
  4. Cedric Yoedt, Soft errors in memories, May 2005 (currently Master’s student at PSU)
  5. Jacek T. Turowski, Interfacing Multi FPGA Platforms, Spring 2007.
  6. Eugene Gallagher, BS/CSE Honors Thesis,  May 2009, LADAR Control System