Research (Active Projects)
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System design using Emerging Devices
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There are several ongoing research projects in our group related to energy efficient nanoelectronics. Broadly, our research efforts are directed at developing novel systems employing emerging devices and circuits. We are investigating the use of a gamut of emerging logic and memory devices including inter-band tunnel transistors, STT-RAM and PCRAM. Different aspects of this research are funded by various agencies including the the NRI (Nanoelectronics Research Initiative) and SRC under the MIND research center, National Science Foundation (Awards 1028807 & 0829926) |
Selected Publications
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Sub Hundred Millivolt Supply Voltage Logic Architecture
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Many emerging nanoscale devices, charge or alternate state variable based, exhibit low transconductance and output resistance under very low operating voltage conditions, making it essential to reconsider device design in conjunction with new logic representation. To circumvent the limited device gain related issues at low voltages, we are exploring a novel interconnectless binary decision diagram (BDD) based logic architecture based on 2 classes of building blocks such as wrapped gate nanowires and split gate nanodots. The proposed architecture produces a) lower device count than conventional Boolean CMOS logic, b) reduces wiring related energy loss, maintains logic functionality under tens of millivolts of supply voltage, and c) operates with ultra-low energy-delay product. All combinational functions can be realized with the nanodot-based BDD approach and sequential logic functions such as latches, shift registers, flipflops can be realized by interfacing with feedback circuits using nanowire transistors. Our ongoing theoretical and experimental research is investigating whether the aggregate can better the projected state of the art for CMOS for the entire range of information processing tasks. This program is supported by a federal government agency. |
Selected Publications
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Embedded Neuromorphic Vision Systems
The algorithmic abstractions for the visual cortex are arguably the best understood portions of the human brain. In the last three decades, neuroscientists have made a number of breakthroughs in understanding the ventral and dorsal paths of the human's visual cortex. These advances have inspired a number of algorithms for computer vision – collectively referred to as “neuromorphic vision algorithms” – which have the potential to provide an unprecedented improvement in the way computers can analyze and interpret information. Recent improvements in FPGA technology, however, are now enabling these systems to be built while meeting performance, power, and size constraints, and maintaining the flexibility required for algorithm exploration. The goals of this research are two-fold: accelerate the design exploration of neuromorphic implementations and performance acceleration of the resulting designs. We have developed several experimental systems that have been field-tested as part of the DARPA NeoVision II program. These systems show speedups of several factors over comparable CPU implementations and higher performance-per-watt over competing GPU implementations. This work is supported by the DARPA Neovision2 program and performed in collaboration with HRL, Teledyne and USC.
Selected Publications
- DeBole, M., A. Al Maashri, M. Cotter, C-L Yu, C. Chakrabarti, V. Narayanan. November 2011. A Framework for Accelerating Neuromorphic-Vision Algorithms on FPGAs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011).
- Cho, Y, S. Bae, Y. Jin, K. M. Irick, V. Narayanan. September 2011. Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. FPL 2011: 311-316
Heterogeneous Stacked 3D Chip Multiprocessors
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With all major chip vendors projecting increased number of cores as the key to their future road maps, innovations in chip multiprocessors is critical. Enabling heterogeneous computing can largely reduce energy costs of computing, while making it more powerful and dependable. Heterogeneous multicores/Chip Multiprocessors (CMPs) are envisioned to be a key design paradigm to combat the challenges of power, memory, and reliability walls that are impeding chip design using deep sub-micron technology. Our group focuses on exploring technology and architectural diversity in designing future heterogeneous architectures with focus on using stacked 3D technology. Our work encompasses memory, on-chip networks and processor logic heterogeneity. This work is supported by National Science Foundation (awards 0903432 & 1147388) |
Selected Publications
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Improving Lifetime Reliability for Reconfigurable Embedded Systems
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Field Programmable Gate Arrays (FPGAs) are used in a variety of embedded applications in communication, space, automotive, medical devices and industrial control. Due to the safety-critical nature of many of these applications, the trustworthiness of the underlying hardware platform is imperative. FPGA-based embedded systems offer lower cost and reduced power consumption by aggressively embracing newer deep sub-micron technology process, which brings lifetime reliability concerns of the systems to the forefront. The impact of performance degradation is more significant in new technologies, resulting in accelerated aging and premature failures. Further, the reconfigurable nature of FPGAs and the heterogeneous components embedded in a FPGA make the reliability degradation and possible solutions to mitigate them different from those employed for application specific integrated circuits and microprocessors. Consequently, techniques to mitigate the impact of aging mechanisms are vital to ensure the trustworthiness of reconfigurable embedded systems, and are the focus of this research. The tools and techniques developed as part of this research serve as a foundation for designing life-time aware reliable embedded systems and for catalyzing further research in this area. Due to the pervasiveness of embedded systems, providing solutions to improve lifetime reliability is anticipated to have a broad impact on the society. This work is supported by National Science Foundation (Award #0916887) |
Selected Publications
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Hardware Accelerators for Vision and Perception
There are many emerging applications in vision and perception that are seamlessly becoming part of our day-to-day life. Both neuromorphic and machine-learning based vision algorithms have been used to drive a diverse range of applications including gaining shopper insights, education assessment and intelligent surveillance. Many of these application domains impose stringent size, weight, performance, and power constraints. Consequently, the design of power-efficient and flexible hardware accelerators is the focus of this research. The focus of our planned exploration is to identify common hardware primitives and data flow patterns across a variety of high-level vision and perception. Based on this exploration, we will compose a core that consists of the identified hardware primitives with adaptive control flows. A programmable instruction set will be developed to support applications in the vision/perception domain. We expect such custom accelerators to be critical for achieving required energy-efficiencies in future generation of Intel processors
Selected Publications
- Michael DeBole, Chi-Li Yu, Ahmed Al Maashri, Matthew Cotter, Chaitali Chakrabarti, Vijaykrishnan Narayanan. “FPGA-Accelerator System for Computing Biologically-Inspired Feature Extraction Models”. Asilomar Conference on Signals, Systems, and Computers. Pacific Grove, CA, November 2011
- A. Al Maashri, M. DeBole, C.-L. Yu, V. Narayanan, C. Chakrabarti. “A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms”. IEEE Workshop on Signal Processing Systems (SiPS 2011). October 2011.
- S. Bae, Y. Cho, S. Park, K. Irick, Y. Jin, N. Vijaykrishnan. “An FPGA implementation of Information Theoretic Visual-Saliency System and Its Optimization”. FCCM 2011.