Publications
Selected publications (2006 - 2011)
2011
2010 2009
2008 2007
2006
Books
Book Chapters
Technical Reports
2011
Journals
Yang, S., P. Gupta, M. Wolf, D. Serpanos, Y. Xie, N. Vijaykrishnan. Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. To appear in ACM Transactions in Embedded Computing Systems (TECS).
Saripalli, V., G. Sun, A. Mishra, Y. Xie, S. Datta and N. Vijaykrishnan. June 2011. Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1(2). (INVITED)
Wang, F. Y. Chen, C. Nicopoulos, X. Wu, Y. Xie, N. Vijaykrishnan. 2011. Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307.
D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu and S. Datta. Feb 2011. Experimental Staggered-Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities. Applied Physics Express, Vol. 4, pp. 024105, February 2011
Conferences
Liu, L., V. Saripalli, V. Narayanan and S. Datta, Dec 2011. Device Circuit Co-Design Using Classical and Non-Classical III-V Multi-Gate Quantum-Well FETs (MuQFETs).2011 IEEE International Electron Devices Meeting (IEDM).
Mohata, D. K., R. Bijesh , S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. Fastenau, D. Loubychev, A. Liu and S. Datta. Dec 2011. Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications. IEEE International Electron Devices Meeting (IEDM)
DeBole, M., C-L Yu, A. Al Maashri, M. Cotter, C. Chakrabarti, V. Narayanan. November 2011. FPGA-Accelerator System for Computing Biologically-Inspired Feature Extraction Models. Asilomar Conference on Signals, Systems, and Computers.
DeBole, M., A. Al Maashri, M. Cotter, C-L Yu, C. Chakrabarti, V. Narayanan. November 2011. A Framework for Accelerating Neuromorphic-Vision Algorithms on FPGAs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011).
Al Maashri, A., M. DeBole, C.-L. Yu, V. Narayanan, C. Chakrabarti. October 2011. A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms. IEEE Workshop on Signal Processing Systems (SiPS 2011). October 2011.
Cho, Y, S. Bae, Y. Jin, K. M. Irick, V. Narayanan. September 2011. Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. FPL 2011: 311-316
Swaminathan K., E. Kultursay, V. Saripalli, V. Narayanan, M. Kandemir and S. Datta, August 2011 Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores International Symposium on Low Power Electronics and Design (ISLPED).
Swaminathan, K., R. Mukundrajan, N. Soundararajan, V. Narayanan. July 2011. Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. ISVLSI 2011: 236-241
Chen, H-W, S. Srinivasan, Y. Xie, V. Narayanan. July 2011. Impact of Circuit Degradation on FPGA Design Security. ISVLSI 2011: 230-235
Park, S., S. Kestur, K. M. Irick and V. Narayanan. Accelerating Neuromorphic Vision on FPGAs. Embedded Computer Vision Workshop (in Conjunction with CVPR) (Invited)
Saripalli, V., J. P. Kulkarni, N. Vijaykrishnan and S. Datta, June 2011. Variation-Tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design", IEEE/ACM Intl. Symp. on Nanoscale Architectures (NanoArch).
Mishra, A. K., X. Dong, G. Sun, Y. Xie, N. Vijaykrishnan, C. R. Das. June 2011 Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80
Mishra, A. K, N. Vijaykrishnan, C. R. Das. June 2011. A case for heterogeneous on-chip interconnects for CMPs. ISCA 2011: 389-400
Kestur, S., K. M. Irick, S. Park, A. Al-Maashri, V. Narayanan, C. Chakrabarti: June 2011. An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. IEEE/ACM Design Automation Conference DAC 2011: 585-590
Saripalli, V., A. K. Mishra, N. Vijaykrishnan and S. Datta. June 2011. An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS Cores", IEEE/ACM Design Automation Conference (DAC).
Chen, Y-C, S. Eachempati, C-Y Wang, S. Datta, Y. Xie, V. Narayanan. June 2011. Automated mapping for reconfigurable single-electron transistor arrays. IEEE/ACM Design Automation Conference DAC 2011: 878-883
Liu, L., V. Saripalli, V. Narayanan and S. Datta, June 2011. Experimental Investigation of Scalability and Transport in In0:7Ga0:3As Multi-Gate Quantum Well FET (MuQFET). 69th Device Research Conference (DRC).
Vijaykrishnan N., V. Saripalli, K. Swaminathan, R. Mukundrajan, G. Sun, Y. Xie, S. Datta. May 2011. Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI 2011: 439-444 (Invited)
Bae, S. Y. Cho, S. Park, K M. Irick, Y Jin, V. Narayanan. May 2011. An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization. FCCM 2011: 41-48
Kestur, S , D. Dantara, V. Narayanan. March 2011. SHARC: A streaming model for FPGA accelerators and its application to Saliency. DATE 2011: 1237-1242
Liu, L., V. Saripalli, E. Hwang, V. Narayanan and S. Datta. May 2011. Multi-Gate Modulation Doped In0.7Ga0.3As Quantum Well FET for Ultra Low Power Digital Logic. 219th Electro chemical Society (ECS) Meeting.
2010
Journals
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Physics Research A. Volume 652(1) p. 370-373
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A. 652(1), p. 338-341
Yu, C-L, K. Irick, C. Chakrabartihakrabarti, V. Narayanan. December 2010. Multidimensional DFT IP Generator for FPGA Platforms. IEEE Transactions on Circuits and Systems. Online at IEEE Explore – Digital Object Identifier 10.1109/TCSI.2010.2078750.
Mishra A.K, A. Yanamandra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan and C. Das. December 2010. RAFT: A Router Architecture with Frequency Tuning for On-chip Networks. Journal of Parallel and Distributed Computing. Online at Elsevier Science – Digital Object Identifier:10.1016/j.jpdc.2010.09.005.
Saripalli, V, L. Liu, S. Datta, and V. Narayanan. October 2010. Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits. Journal of Low Power Electronics 6:415-428.
Nicopoulos, C. A., S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. July-September 2010. On the Effects of Process Variation in Network-on-Chip Architectures. IEEE Transactions on Dependable and Secure Computing (TDSC) 7(3):240-254.
Mookerjea, S., D. Mohata, T. Mayer, N. Vijaykrishnan, S. Datta. June 2010. Temperature-Dependent I-V Characteristics of a Vertical In0.53Ga0.47AS Tunnel FET. IEEE Electron Device Letters 31(6):564-566.
Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2010. Total Power Optimization for Combinational Logic Using Genetic Algorithms. Journal of VLSI Signal Processing Systems 58(2):145-160.
Conferences
Bae, S. M., N. Vijaykrishnan. August 2010. Thermal Gradient Aware Clock Skew Scheduling for FPGAs. Proceedings of the Twentieth International Conference on Field Programmable Logic and Applications (FPL 2010). pp. 101-106. Milano, Italy.
Sampath Kumar, V., K. Irick, A. Al Maashri, N. Vijaykrishnan. July 2010. A Scalable Bandwidth Aware Architecture for Connected Component Labeling. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010). pp. 116-121. Lixouri Kefalonia, Greece.
Vijaykrishnan, N., A. Al Mashri, K. Irick, M. DeBole, S. Park. July 2010. AutoFLEX: A Framework for Image Processing Applications on Multi-FPGA Systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2010). pp. 59-66. Las Vegas, NV. (Invited)
Soundararajan, N., A. Sivasubramaniam, N. Vijaykrishnan. June 2010. Characterizing Soft-error Vulnerability of Mulicores Running Multi-threaded Applications. Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2010). pp. 379-380. New York, NY.
Saripalli, V., D. K. Mohata, S. Mookerjea, S. Datta, N. Vijaykrishnan. June 2010. Low Power Loadless 4T SRAM Cell Based on Degenerately Doped Source (DDS) In_0.53 GA_0.47 as Tunnel FETs. Proceedings of the IEEE Device Research Conference (DRC 2010). pp. 101-102.
Datta, S., A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, N. Vijaykrishnan. , June 2010. "Non-silicon Logic Elements on Silicon for Extreme Voltage Scaling," Proceedings of the Silicon Nanoelectronics Workshop (SNW), pp.15-16, Honolulu, Hawaii
Kestur, S., S. Park, K. Irick, N. Vijaykrishnan. May 2010. Accelerating the Nonuniform Fast Fourier Transform Using FPGAs. Proceedings of the Eighteenth IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2010). pp. 19-26. Charlotte, NC.
Kandemir, M., O. Ozturk, S. Narayanan, M. J. Irwin. April 2010. Compiler Directed Communication Reliability Enhancement for Chip Multiprocessors. Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2010). pp. 85-94. Stockholm, Sweden.
Yu, C.-L., C. Chakrabarti, S. Park, N. Vijaykrishnan. March 2010. Bandwidth-intensive FPGA Architecture for Multi-dimensional DFT. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2010). pp. 1486-1489. Dallas, TX.
Ricketts, A., N. Vijaykrishnan, J. Singh, D. Pradhan. March 2010. Investigating the Impact of NBTI on Different Power Saving Cache Strategies. Proceedings of the Design, Automation & Test in Europe (DATE 2010). pp. 592-597. Dresden, Germany.
Rathi, A., M. DeBole, W. Ge, R. Collins, N. Vijaykrishnan. March 2010. A GPU Based Implementation of Center-Surround Distribution Distance for Feature Extraction and Matching. Proceedings of the Design, Automation & Test in Europe (DATE 2010). pp. 172-177. Dresden, Germany.
Yanamandra, A., S. Eachempati, N. Soundararajan, N. Vijaykrishnan, M. J. Irwin, R. Krishnan. January 2010. Optimizing Power and Performance for Reliable On-Chip Networks. Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010). pp. 431-436. Taipei, Taiwan.
Singh, J., R. Krishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan. January 2010. A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications. Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010). pp. 181-186. Taipei, Taiwan.
Saripalli, V., N. Vijaykrishnan, S. Datta. January 2010. Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. Proceedings of the Twenty-Third International Conference on VLSI Design (VLSI Design 2010). pp. 399-404. Bangalore, India.
2009
Journals
Kim, J. SKim, J. S., P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. December 2009. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Transactions on Computers 58(12):1654-1667.
Mookerjea, S., R. Krishnan, S, Datta, N. Vijaykrishnan. October 2009. On Enhanced Miller Capacitance Effect in Inter-Band Tunnel Transistors. IEEE Electron Device Letters 30(10):1102-1104.
Mookerjea, S., R. Krishnan, S. Datta, N. Vijaykrishnan. September 2009. Effective Output Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation. IEEE Transactions on Electron Devices 56(9):2092-2098.
DeBole, M., R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. August 2009. New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4):417-431.
Ramanarayanan, R., V. Degalahal, R. Krishnan, J. Kim, N. Vijaykrishnan, Y. Xie, M. Irwin, K. Unlu. July-September 2009. Modeling Soft Errors at Device and Logic Level for Combinational Circuits. IEEE Transactions on Dependable and Secure Computing (TDSC) 6(3):202-216.
Hu, J., F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. July 2009. Compiler-assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems. ACM Transactions on Embedded Computing Systems 8(4):27.1-27.29.
Mutyam, M., F. Wang, R. Krishnan, N. Vijaykrishnan, M. Kandemir, Y. Xie, M. J. Irwin. July 2009. Process Variation Aware Adaptive Cache Architecture and Management. IEEE Transactions on Computers 58(7):865-877.
Eachempati, S., N. Vijaykrishnan, A. Nieuwoudt, Y. Massoud. April 2009. Predicting the Performance and Reliability of Future Field Programmable Gate Arrays Routing Architectures with Carbon Nanotube Bundle Interconnect. IET Circuits, Devices, & Systems 3(2):64-75.
Ragheb, T., A. Ricketts, M. Modal, S. Kirolos, G. Link, N. Vijaykrishnan, Y. Massoud. February 2009. Design of Thermally Robust Clock Trees using Dynamically Adaptive Clock Buffers. IEEE Transactions on Circuits and Systems (TCAS) 56(2):374-383.
Conferences
Mookerjea, S., D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, N. Vijaykrishnan, D. Schlom, A. Liu, S. Datta. December 2009. Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications. Proceedings of the IEEE International Electron Devices Meeting (IEDM 2009). 3 pages. Baltimore, MD.
Mishra, A., R. Das, S. Eachempati, N. Vijaykrishnan, C. R. Das. December 2009. A Case for Dynamic Frequency Tuning in On-Chip Networks. Proceedings of the Forty-Second International Symposium on Microarchitecture (MICRO-42). pp. 292-303. New York, NY.
Saripalli, V., N. Vijaykrishnan, S. Datta. October 2009. Ultra Low Energy Binary Decision Diagram Circuits using Few Electron Transistors. Proceedings of the Workshop on Nano-Bio Sensing Paradigms and Applications, in conjunction with Nano-Net 2009. pp. 200-209. Luzern, Switzerland.
Al Maashri, A., G. Sun, X. Dong, N. Vijaykrishnan, Y. Xie. October 2009. 3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis. Proceedings of the International Conference on Computer Design (ICCD 2009). pp. 254-259. Lake Tahoe, CA.
Kim, J.S., C.-L. Yu, L. Deng, S. Kestur, N. Vijaykrishnan, C. Chakrabarti. October 2009. FPGA Architecture for 2D Fast Fourier Transform Based on 2D Decomposition for Large-Sized Data. Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2009). pp. 121-126. Tampere, Finland.
Irick, K., M. DeBole, S. Park, N. Vijaykrishnan. August 2009. A Scalable Multi-FPGA Framework for Real-time Digital Signal Processing. Proceedings of SPIE Optics+Photonics Conference. 6 pages. San Diego, CA.
Datta, S., N. Vijaykrishnan. August 2009. Green Transistors to Green Architectures. Proceedings of the 2009 International Symposium on Low Power Electronics and Design (ISLPED 2009). pp. 429-430. San Francisco, CA.
Xie, Y., S. Eachempati, A. Yanamandra, N. Vijaykrishnan, M. J. Irwin. July 2009. Power and Area Reduction using Carbon Nanotube Bundle Interconnect in Global Clock Tree Distribution Network. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009). pp. 51-56. San Francisco, CA.
Bae, S., R. Krishnan, N. Vijaykrishnan. May 2009. A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009). pp. 193-198. Tampa, FL.
Mangalagiri, P., N. Vijaykrishnan. May 2009. Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009). pp. 61-66. Tampa, FL.
Bae, S., P. Mangalagiri, N. Vijaykrishnan. April 2009. Exploiting Clock Skew Scheduling for FPGA. Proceedings of the Design Automation & Test in Europe (DATE 2009). pp. 1524-1529. Nice, France.
Das, R., S. Eachempati, A. K. Mishra, N. Vijaykrishnan, C. R. Das. February 2009. Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs. Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture (HPCA-15). pp. 175-186. Raleigh, NC.
Yanamandra, A., M. J. Irwin, N. Vijaykrishnan, M. Kandemir, S. H. K. Narayanan. January 2009. In-Network Caching for Chip Multiprocessors. Proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2009). Springer-Verlag LNCS 5409:373-388. Paphos, Cyprus.
Sridharan, S., M. DeBole, G. Sun, Y. Xie, N. Vijaykrishnan. January 2009. A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner. Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009). pp. 763-768. Yokohama, Japan.
DeBole, M., R. Krishnan, V. Balakrishnan, W. Wang, L. Hong, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. January 2009. A Framework for Estimating NBTI Degradation of Microarchitectural Components. Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009). pp. 455-460. Yokohama, Japan.
Henkel, J., N. Vijaykrishnan, S. Parameswaran, R. Ragel. January 2009. Security and Dependability of Embedded Systems: A Computer Architects’ Perspective. Proceedings of the Twenty-Second International Conference on VLSI Design (VLSI Design 2009). pp. 30-32. New Delhi, India.
2008
Journals
Srinivasan, S., F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2008. Exploring Architectural Solutions for Energy Optimizations in Bus Based SoC. IET Computers & Digital Techniques 2(5):347-354.
Celik, C., K. Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M. J. Irwin, Y. Xie. August 2008. Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear Chemistry 278(2):509-512.
Gayasen, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. July 2008. Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Transactions on VLSI 16(7):882-893.
Yang, S., Yang, S., W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, Y. Xie. July 2008. Case Study of Reliability-Aware and Low-Power Design. IEEE Transactions on Very Large Scale Integration (VLSI) 16(7):861-873.
Srinivasan, S., R. Krishnan, P. Mangalagiri, Y. Xie, N. Vijaykrishnan, M. J. Irwin, K. Sarpatwari. April-June 2008. Toward Increasing FPGA Lifetime. IEEE Transactions on Dependable and Secure Computing 5(2):115-127.
Tsai, Y., F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. April 2008. Design Space Exploration for Three-Dimensional Cache. IEEE Transactions on VLSI 16(4):444-455.
Conferences
Mangalagiri, P., S. Bae, R. Krishnan, N. Vijaykrishnan, Y. Xie, T. Tuan. November 2008. Thermal-Aware Reliability Analysis for Platform FPGAs. Proceedings of the International Conference on Computer Aided Design (ICCAD 2008). pp. 722-727. San Jose, CA.
Ramakrishnan, K., N. Vijaykrishnan, Y. Xie. October 2008. Comparative Analysis of NBTI Effects on Low Power and High Performance Flip-Flops. Proceedings of the XXVI International Conference on Computer Design (ICCD 2008). pp. 200-208. Lake Tahoe, CA.
Deng, L., C-L. Yu, C. Chakrabarti, J. Kim, N. Vijaykrishnan. October 2008. Efficient Image Reconstruction Using Partial 2D Fourier Transform. Proceedings of the 2008 IEEE Workshop on Signal Processing Systems (SIPS 2008). pp. 49-54. Washington, D.C.
Soundararajan, N., N. Vijaykrishnan, A. Sivasubramaniam. August 2008. Impact of DVFS on the Architectural Vulnerability of GALS Architctures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2008). pp. 351-356. Bangalore, India.
Soundararajan, N., A. Yanamandra, C. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. June 2008. Analysis and Solutions to Issue Queue Process Variation. Proceedings of the Thirty-Eighth Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2008). pp. 11-21. Anchorage, Alaska.
Park, D., S. Eachempati, R. Das, A. K Mishra, N. Vijaykrishnan, Y. Xie, C. R Das. June 2008. MIRA: A Multi-Layered On-Chip Interconnect Router Architecture. Proceedings of the International Symposium on Computer Architecture (ISCA 2008). pp. 251-261. Beijing, China.
Eachempati, S., V. Saripalli, N. Vijaykrishnan, S. Datta. June 2008. Reconfigurable BDD Based Quantum Circuits. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch 2008). pp. 61-67. Anaheim, CA.
Mangalagiri, P., K. Sarpatwari, A. Yanamandra, N. Vijaykrishnan, Y. Xie, M. J. Irwin, O. A. Karim. May 2008. A low-power Phase Change Memory Based Hybrid Cache Architecture. Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2008). pp. 395-398. Orlando, FL.
Irick, K., N. Vijaykrishnan, M. DeBole, A. Gayasen. April 2008. A Hardware Efficient Support Vector Machine Architecture for FPGA. Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008). pp. 304-305. Stanford, CA.
Krishnan, R., R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, K. Unlu. March 2008. Hierarchical Soft Error Estimation Tool (HSEET). Proceedings of the Ninth International Symposium on Quality Electronic Design (ISQED 2008). pp. 680-683. San Jose, CA.
Das, R., A. K. Mishra, C. Nicopoulos, D. Park, N. Vijaykrishnan, R. Iyer, C. R. Das. February 2008. Performance and Power Optimization through Data Compression in Network-on-Chip Architectures. Proceedings of the Fourteenth International Symposium on High Performance Computer Architecture (HPCA 2008). pp. 215-225. Salt Lake City, UT.
Atienza, D., G. De Micheli, L. Benini, J. L. Ayala, P. G. Del Valle, M. DeBole, N. Vijaykrishnan. January 2008. Reliability-Aware Design for Nanometer-Scale Devices. Proceedings of the Thirteenth IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2008). pp. 549-554. Seoul, Korea.
2007
Journals
Brooks, R., P. Govindaraju, M. Pirretti, N. Vijaykrishnan, M. Kandemir. November 2007. On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Transactions on Systems, Man, and Cybernetics 37(6):1246-1258.
Xie, Y., L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. October 2007. Reliability-Aware Co-synthesis for Embedded Systems. Journal of VLSI Signal Processing 49(1):87-99.
Wang, F., M. Debole, X. Wu, Y. Xie, N. Vijaykrishnan, M. J. Irwin. September 2007. On-chip Bus Thermal Analysis and Optimization. IET Computer & Digital Techniques 1(5):590-599.
Kim, S., Kim, S., N. Vijaykrishnan, M. J. Irwin. August 2007. Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set Resolution. Microprocessors and Microsystems 31(5):293-301.
Hu, J., N. Vijaykrishnan, M. J. Irwin, M. Kandemir. July 2007. Optimizing Power Efficiency in Trace Cache Fetch Unit. IET Computers and Digital Techniques 1(4):334-348.
Gayasen, S. Srinivasan, N. Vijaykrishnan, M. Kandemir. 2007. Design of Power-Aware FPGA Fabrics. International Journal of Embedded Systems 3(1/2):52-64.
Li. T., J. Rubio, L. K. John, A. Sivasubramaniam, N. Vijaykrishnan. January 2007. OS-aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Transactions on Computers 56(1):2-17.
Conferences
Irick, K., M. DeBole, N. Vijaykrishnan, R. Sharma, H. Moon, S. Mummareddy. August 2007. A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007). pp. 267-272. Amsterdam, Netherlands.
Kim, J., P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. August 2007. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform. Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007). pp. 68-73. Amsterdam, Netherlands.
Park, D., R. Das, C. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, C. R. Das. August 2007. Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Proceedings of the Fifteenth Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007). pp. 15-20. Stanford, CA.
Kim, J., C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, C. R. Das. June 2007. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Proceedings of the Thirty-Fourth Annual International Symposium on Computer Architecture (ISCA 2007). pp. 138-149. San Diego, CA.
Ricketts, A., M. Mutyam, N. Vijaykrishnan, M. J. Irwin. May 2007. Investigating Simple Low Latency Reliable Multiported Register Files. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007). pp. 375-382. Porte Alegre, Brazil.
Mondal, M., A. Ricketts, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan, Y. Massoud. April 2007. Thermally Robust Clocking Schemes for 3D Integrated Circuits. Proceedings of the Design, Automation and Test in Europe (DATE'07). pp. 1206-1211. Nice, France.
Mutyam, M., N. Vijaykrishnan. April 2007. Working with Process Variation Aware Caches. Proceedings of the Design, Automation and Test in Europe (DATE'07). pp. 1152-1157. Nice, France.
Eachempati, S., A. Nieuwoudt, A. Gayasen, Y. Massoud, N. Vijaykrishnan. April 2007. Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. Proceedings of the Design, Automation and Test in Europe (DATE'07). pp. 307-312. Nice, France.
Krishnan, R., R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2007. Variation Impact on SER of Combinational Circuits. Proceedings of the International Society for Quality Electronic Design (ISQED 2007). pp. 911-916. San Jose, CA.
Mupid, A., M. Mutyam, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2007. Variation Analysis of CAM Cells. Proceedings of the Eighth International Symposium on Quality Electronic Design (ISQED 2007). pp. 333-338. San Jose, CA.
Mondal, M., A. Ricketts, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan, Y. Massoud. March 2007. Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. Proceedings of the International Society for Quality Electronic Design (ISQED 2007). pp. 67-72. San Jose, CA.
Ramakrishnan, R S. Srinivasan, N. Vijaykrishnan, Y. Xie. January 2007. Impact of NBTI on FPGAs. Proceedings of the International Conference on VLSI Design. pp. 717-722. Bangalore, India.
Vaidyanathan, B., W. Hung, F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. January 2007. Architecting Microprocessor Components in 3D Design Space. Proceedings of the Twentieth International Conference on VLSI Design. pp. 103-108. Bangalore, India.
2006
Journals
Pirretti, M., S. Zhu, N. Vijaykrishnan, P. McDaniel, M. Kandemir, R. Brooks. September 2006. The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. International Journal of Distributed Sensor Networks 2(3):267-287.
Lee, J., N. Vijaykrishnan, M. J. Irwin. July 2006. Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding. IEEE Transactions on Signal Processing 54(7):2559-2566.
Lee, J., N. Vijaykrishnan, M. J. Irwin. May 2006. Efficient VLSI Implementation of Inverse Discrete Cosine Transform. IEEE Transactions on Circuits and Systems for Video Technology 16(5):655-662.
Lee, J., N. Vijaykrishnan, M. J. Irwin, W. Wolf. February 2006. An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain. IEEE Transactions on Circuits and Systems for Video Technology 16(2):191-201.
Zhang, W.,Zhang, W., Y-F Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2006 Reducing Dynamic and Leakage energy in VLIW Architectures. ACM Transactions on Embedded Computing Systems 5(1):1-28.
Vijaykrishnan, N., Xie, Y. January 2006. Reliability concerns in embedded system designs. IEEE Computer. 39(1):118-120. (Invited)
Conferences
Nicopoulos, C. A., D. Park, J. Kim, N. Vijaykrishnan, C. R. Das. December 2006. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. Proceedings of the International Symposium on Microarchitecture (MICRO 06). pp. 333-346. Orlando, FL.
Vaidyanathan, B., Y. Xie, N. Vijaykrishnan, R. Luo. December 2006. Leakage Optimized DECAP Design for FPGAs. Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006). pp. 960-963. Singapore.
Sundararajan, P. A. Gayasen, N. Vijaykrishnan, T. Tuan. November 2006. Thermal Characterization and Optimization in Platform FPGAs. Proceedings International Conference on Computer Aided Design (ICCAD-2006). pp. 443-447. San Jose, CA.
Sundararajan, P, S. Krishnamurthy, N Vijaykrishnan, K. Chaudhary, R. Jayaraman. September 2006. Performance Improvements Through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). pp. 105-106. Austin, TX.
Chen, G, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan. September 2006. Using Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). pp. 113-114. Austin, TX.
Srinivasan, S., R. Ramadoss, N. Vijaykrishnan. September 2006. Process Variation Aware Parallelization Strategies for MPSoCs. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). pp. 179-184. Austin, TX.
Park, D., C. Nicopoulos, J. Kim, N. Vijaykrishnan, C. R. Das. September 2006. A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects. Proceedings of the First International Conference on Nano-Networks (Nano-Net 2006). CDROM proceedings. 6 pages. Lausanne, Switzerland.
Srinivasan, S., M. Prasanth, S. Karthink, Y. Xie, N. Vijaykrishnan. July 2006. FLAW: FPGA Lifetime Awareness. Proceedings of the Forty-Third Design Automation Conference (DAC 2006). pp. 630-635. San Francisco, CA.
Park, D., C. A. Nicopoulos, J. Kim, N. Vijaykrishnan, C. R. Das. June 2006. Exploring Fault-Tolerant Network-on-Chip Architectures. Proceedings of the International Conference on Dependable Systems and Networks – DCCS Track (DSN-2006). pp. 93-102. Philadelphia, PA.
Li, F., C. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan, M. Kandemir. June 2006. Design and Management of 3D Chip Multiprocessors using Network-in-memory. Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006). pp. 130-141. Boston, MA.
Kim, J., C. A. Nicopoulos, D. Park, N. Vijaykrishnan, C. R. Das. June 2006. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006). pp. 4-15. Boston, MA.
Mutyam, M., F. Li, N. Vijaykrishnan, M. Kandemir, M.J. Irwin. June 2006. Compiler Directed Thermal Management for VLIW Functional Units. Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006). pp. 163-172. Ottawa, Canada.
Gayasen, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. April 2006. Switch Box Architectures for Three-Dimensional FPGAs. Proceedinsg of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 2 pages. Napa Valley, CA.
Ramanarayanan, R., Krishnan, N. Vijaykrishnan, Y. Xie, M. J. Irwin. April 2006. Temperature and Voltage Scaling Effects on Electrical Masking. Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006). 4 pages. Urbana, IL.
Vaidyanathan, B., Y. Xie, N. Vijaykrishnan, H. Zheng. April 2006. Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits. Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006). 4 pages. Urbana, IL.
Lin, I., S. Srinivasan, N. Vijaykrishnan, N. Dhanwada. March 2006. Transaction Level Error Susceptibility Model for SoC Bus Based SoC Architectures. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 775-780. San Jose, CA.
Link, G., N. Vijaykrishnan. March 2006. Thermal Trends in Emerging Technologies. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 625-632. San Jose, CA. (Nominated for Best Paper Award)
Hung, W.-L., G. Link, Y. Xie, N. Vijaykrishnan, M. J. Irwin. March 2006. Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 98-104. San Jose, CA.
Wang, F., Y. Xie, N. Vijaykrishnan, M. J. Irwin. March 2006. On-chip Bus Thermal Analysis and Optimization. Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006). pp. 850-855. Munich, Germany.
Ricketts, A. J., K. Irick, N. Vijaykrishnan, M. J. Irwin. March 2006. Priority Scheduling in Digital Microfluidics-Based Biochips. Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006). pp. 329-334. Munich, Germany.
Kim, J., C. A. Nicopoulos, D. Park, N. Vijaykrishnan, C. R. Das. March 2006. Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures. Special Workshop on Future Interconnects and Networks on Chip, in conjunction with the Design, Automation and Test in Europe (DATE 06). Proceedings on CD-ROM. Munich, Germany.
Theocharides, T., N. Vijaykrishnan, M. J. Irwin. March 2006. A Parallel Architecture for Hardware Face Detection. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006). pp. 452-454. Karlsruhe, Germany.
Srinivasan, S., N. Vijaykrishnan. March 2006. Variation Aware Placement Scheme for FPGAs. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). pp. 422-424. Karlsruhe, Germany.
Mutyam, M., M. Eze, N. Vijaykrishnan, Y. Xie. March 2006. Delay and Energy Efficient Data Transmission for On-Chip Buses. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006). pp. 355-360. Karlsruhe, Germany.
Yang, S., W. Wolf, N. Vijaykrishnan, Y. Xie. March 2006. Reliability-aware SOC Voltage Islands Partition and Floorplan. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). pp. 341-347. Karlsruhe, Germany.
Chen, G., G. Chen, M. Kandemir, N. Vijaykrishanan, M. J. Irwin. January 2006. Object Duplication for Improving Reliability. Proceedings of the Eleventh Asia and South Pacific Design Automation Conference (ASP-DAC 2006). pp. 140-145. Yokohama City, Japan.
Richardson, T., C. Nicopolus, N. Vijaykrishnan, D. Park, Y. Xie C. R. Das. January 2006. A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. Proceedings of IEEE International Conference on VLSI Design. pp. 657-664. Bangalore, India.
Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin. January 2006. SEAT-LA: A Soft Error Analysis tool for Combinational Logic. Proceedings of Nineteenth International Conference on VLSI Design. pp. 499-502. Bangalore, India.
Irick, K., T. Theocharides, N. Vijaykrishnan, M. J. Irwin. October 29-November 1, 2006. Real Time Embedded Face Detection. Proceedings of the Asilomar Conference on Signals, Systems, and Computers. 6 pages. Pacific Grove, CA.
Books
Nicopoulos, C., N. Vijaykrishnan, C. R. Das. October 2009. Network-on-Chip Architectures: A Holistic Design Exploration. 175 pages. Springer.
Books Chapters
Eachempati, S., R. Das, N. Vijaykrishnan, Y. Xie, S. Datta, C. R. Das. February 2011. HeTERO: Hybrid Topology Exploration for RF Based On Chip Networks. To appear in Communication Architectures for Systems-on-Chip. J. L. Ayala, Editor. CRC Press.
Eachempati, S., A. Gayasen, N. Vijaykrishnan, M. J. Irwin. January 2011. Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs. To appear in Nanoelectronic Circuit Design. N. Jha, D. Chen, Editors. Springer.
Kumar, V., K. Irick, A. Maashri, N. Vijaykrishnan. 2011. A Scalable Bandwidth-Aware Architecture for Connected Component Labeling. To appear in Very Large Scale Integration Systems: Emerging Trends & Challenges. N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Editors. Springer.
Eachempati, S., D. Park, R. Das, A. K. Mishra, N. Vijaykrishnan, Y. Xie, C. R. Das. December 2010. Three-Dimensional On-Chip Interconnect Architectures. Designing Network On-Chip Architectures in the Nanoscale Era. J. Flich, D. Bertozzi, Editors. Chapman & Hall/CRC Computational Science.
Maashri, A., G. Sun, X. Dong, Y. Xie, N. Vijaykrishnan. November 2010. Influence of Stacked 3D Memory/Cache Architectures on GPUs. 3D Integration for NoC-based SoC Architectures. Chapter 11, pp. 249-272. A. Sheibanyrad, F. Pétrot, A. Jantsch, Editors. Springer.
Yanamandra, A., S. Eachempati, N. Vijaykrishnan, M. J. Irwin. 2010. Reliability Aware Power Optimizations in DVFS-based On-Chip Networks. Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication. Chapter 11, pp. 277-292. J-S. Shen, P-A. Hsiung, Editors.
Xie, Y., N. Vijaykrishnan, C. R. Das. 2009. Three-Dimensional Network-on-Chip Architectures. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Chapter 8, pp. 189-218. Y. Xie, J. Cong, S. Sapatnekar, Editors. Springer.
Theocharides, T., C. Nicopoulos, K. Irick, N. Vijaykrishnan, M. J. Irwin. 2006. An Exploration of Hardware Architectures for Face Detection. The VLSI Handbook, Second Edition. Chapter 83, pp. 1-27.
Gayasen, A., N. Vijaykrishnan. 2006. Architecture and Design Flow Optimizations for Power-Aware FPGAs. The VLSI Handbook, Second Edition. Chapter 20, pp. 1-15.
Degalahal, V., R. Ramanarayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin. May 2006. Effect of Power Optimizations on Soft Error Rate. VLSI-SoCc: From Systems to Chips. Edited by M. Glesner, H. Eveking, L. Indrusiak, V. Mooney, R. Reis.
Hu, J. S., G. Chen, M. Kandemir, N. Vijaykrishnan. 2006. Software Power Optimisation. System on Chip: Next Generation Electronics. pp. 289-316. Edited by Bashir M. Al-Hashimi.
Technical Reports
Soundararajan, N., M. DeBole, N. Vijaykrishnan, A. Sivasubramaniam, V. Lyubosiavsky. September 2009. Addressing Non-Uniform Aging in Microprocessor Storage Structures. Computer Science and Engineering Technical Report CSE 09-013, The Pennsylvania State University.
Eachempati, S., A. Yanamandra, Y. Xie, N. Vijaykrishnan, M. J. Irwin. February 2008. Power and Area Reduction Using Carbon Nanotube Bundle Interconnect in Global Clock Tree Distribution Network. Computer Science and Engineering Technical Report CSE-08-005. The Pennsylvania State University.
Das, R., C. Nicopoulos, A. Mishra, D. Park, J. Kim, R. Iyler, N. Vijaykrishnan, C. R. Das. July 2007. Exploring the Effects of Data Compression in Network-on-Chip Architectures. Computer Science and Engineering Technical Report CSE-07-010, The Pennsylvania State University.
Nicopoulos, C., S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. July 2007. On the Effects of Process Variation in Network-on-Chip Architectures. Computer Science and Engineering Technical Report CSE-07-009, The Pennsylvania State University.
Link, G., J. Kim, N. Vijaykrishnan, C. R. Das. September 2006. Network-on-Chip (NoC) Architectures: A Resource-Constrained Perspective. Computer Science and Engineering Technical Report CSE-06-014, The Pennsylvania State University.
Kim, J., C. Nicopoulos, D. Park, N. Vijaykrishnan, C. R. Das. September 2006. A Fine-Grained Modular Architecture for System-on-Chip Networks. Computer Science and Engineering Technical Report CSE-06-013, The Pennsylvania State University.