Publications (year wise)

2005 ( Click year for Topical Listing for 2005 )

Journals

  • M. Srinivasan, T. Theocharides, L. Benini, G. DeMicheli, N. Vijaykrishnan and M. J. Irwin. Analysis of Error Recovery Schemes for Network on Chips. To appear IEEE Design and Test.
  • V. Degalahal, L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Soft Errors Issues in Low Power Caches. To appear IEEE Transaction on VLSI.
  • W. Zhang, Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and V. De Leakage-Aware Compilation for VLIW Architectures. To appear IEE Proceedings-Computers and Digital Techniques. (Invited)
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, W. Wolf, ?An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain?, To appear in IEEE Transactions on Circuits and Systems for Video Technology
  • E.J. Kim, G. M. Link, K. H. Yum, N. Vijaykrishnan, M. Kandemir, M. Irwin and C. Das. "A Holistic Approach to Designing Energy-Efficient Cluster Interconnects," IEEE Transactions on Computers, Vol. 54, No. 6, June 2005.
  • S. Yang, Wayne Wolf and Vijaykrishnan N., "Comprehensive Power and Performance Analysis of Motion Estimation Based on Hardware and Software realizations", to appear in IEEE Tran. on Computer, Special issue of Power Efficient Computing 2005
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and A Sivasubramaniam. Compiler-Directed High-Level Energy Estimation and Optimization. ACM Transactions on Embedded Systems, Special Issue on Embedded Software (To appear)
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Exploiting Temporal Loads for Low Latency and High Bandwidth Memory. To appear in IEE Proceedings-Computers and Digital Techniques.
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Optimizing Leakage Energy Consumption in Cache Bitlines. Design Automation for Embedded Systems (DAEM), Vol. 9, Issue 1, pp. 5-18, March 2005

    Conferences

  • S. Srinivasan, F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. Simultaneous Memory and Bus Partitioning for SoC Architectures. IEEE International SoC Conference, September 2005, Washington DC.
  • N. Dhanwada, I. Lin, N. Vijaykrishnan. A Power Estimation Methodology for SystemC Transaction Level Models. International Conference on Hardware/Software Codesign and Synthesis CODES+ISSS, Sept 2005, New Jersey, USA.
  • E. Swankowski and N. Vijaykrishnan. Dynamic High-Performance Multi-Mode Architectures for AES Encryption. 8th Annual MAPLD International Conference, Sept 2005.
  • E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth,V. Kamakoti and N. Vijaykrishnan, "Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs", 12th Reconfigurable Architectures Workshop (RAW 2005), Colorado, USA.
  • E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth,V. Kamakoti and N. Vijaykrishnan, "A CLB architecture for Online correction of SEU-based Errors in LUTs of SRAM-based FPGAs, European Test Symposium (2005), Tallin.
  • E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth,V. Kamakoti and N. Vijaykrishnan, "Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration, European Test Symposium (2005), Tallin. (Appeared earlier as Extended Abstract in 13th ACM International Symposium on Field Programmable Gate Arrays.)
  • E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Detecting SEU-caused Routing Errors in SRAM-based FPGAs", Eighteenth International Conference on VLSI Design, January 2005, Kolkatta, India.
  • E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, "Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs", ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), January 2005, Shanghai, China
  • Hu, J.S.; Feihui Li; Degalahal, V.; Kandemir, M.; Vijaykrishnan, N.; Irwin, M.J.; Compiler-Directed Instruction Duplication for Soft Error Detection. Design, Automation and Test in Europe, 2005. Proceedings 07-11 March 2005 Page(s):1056 - 1057.
  • Y-F. Tsai, N. Vijaykrishnan, Y. Xie, and M.J. Irwin, "Leakage-Aware Interconnect for On-Chip Network", Design, Automation, and Test in Europe, Mar 2005, pp. 230-231.
  • W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, "Thermal-Aware Task Allocation and Scheduling for Embedded Systems", Design, Automation and Test in Europe (DATE), Munich, Germany, March 2005.
  • W.-L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, and M. J. Irwin. "Thermal-Aware Floorplanning Using Genetic Algorithms", International Symposium on Quality Electronic Design (ISQED), San Jose, CA , March 2005.
  • Tsai, Y.-F.; Vijaykrishnan, N.; Xie, Y. and Irwin, M. J.; "Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty", International Conference on VLSI Design, Jan 2005, pp. 374-379.
  • Suresh Srinivasan, Aman Gayasen, Vijaykrishnan N. and Tim Tuan. "Leakage control in FPGA routing fabric." In proceeedings of ASPDAC 2005, Jan 2005.
  • G. M. Link and N. Vijaykrishnan, "Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip," In the Proceedings of Design Automation and Test in Europe (DATE) 2005.
  • Srinivasan, S.; Lin Li; Vijaykrishnan, N.; Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. Design, Automation and Test in Europe, 2005. Proceedings 07-11 March 2005 Page(s):218 - 223
  • Shengqi Yang; Wolf, W.; Vijaykrishnan, N.; Yuan Xie; Wenping Wang. Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits.. 18th International Conference on VLSI Design, 2005, 3-7 Jan. 2005 Page(s):165 - 170
  • T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin, "Implementing LDPC Decoding on Networks on Chip", in the Proceedings of the 18th International Conference on VLSI Design, India, January 2005.
  • J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, C. R. Das, "A Low Latency Router Supporting Adaptivity for On-Chip Interconnects", in the Proceedings of the 42nd Design Automation Conference (DAC), June 2005, Anaheim, CA.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, "High Performance Array Processor for Video Decoding", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2005.
  • S. Yang; Wolf, W.; Vijaykrishnan, N.; Serpanos, D.N.; Yuan Xie; Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. Design, Automation and Test in Europe, 2005. Proceedings 07-11 March 2005 Page(s):64 - 69
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Exploiting Temporal Loads for Low Latency and High Bandwidth Memory. To appear in IEE Proceedings-Computers and Digital Techniques.
  • H. Saputra, O. Ozturk, N. Vijaykrishnan, M. Kandemir, and R. Brooks, "A Data-Driven Approach for Embedded Security", To appear in IEEE Computer Society Annual Symposium on VLSI 2005 (ISVLSI 2005), Tampa, Florida, May 11-12, 2005. 2005
  • A. Gayasen, N. Vijaykrishnan, Mary J. Irwin, "Exploring Technology Alternatives for Nano-Scale FPGA Interconnects," Design Automation Conference (DAC-05), June 2005.
  • Irick, K.M.; Xu, W.; Vijaykrishnan, N.; Irwin, M.J.; A nanosensor array-based VLSI gas discriminator. 18th International Conference on VLSI Design, 2005. 3-7 Jan. 2005 Page(s):241 - 246

    2004 ( Click year for Topical Listing for 2004 )

    Journals/Magazines

  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. An integer linear programming based tool for wireless sensor networks, Journal of Parallel and Distributed Computing (JPDC) (To appear).
  • Y-F. Tsai, D. Duarte, N. Vijaykrishnan and M. J. Irwin. Characterization and modeling of run-time techniques for leakage power reduction. IEEE Transactions on VLSI, Nov 2004
  • G. Chen, B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and R. Chandramouli. Studying energy tradeoffs in off-loading computation/compilation in Java-enabled mobile devices. IEEE Transactions on Parallel and Distributed Systems (TPDS). Vol 15, No. 9, pp. 795-809, Sept 2004.
  • J. Hu, M. Kandemir, N. Vijaykrishnan and M. J. Irwin. To appear. Analyzing Data Reuse for Cache Reconfiguration. ACM Transactions on Embedded Computing Systems
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. To appear. Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy. ACM Transactions on Architecture and Code Optimization (TACO). pp. 3 - 33, Volume 1, issue 1, March 2004.
  • W. Zhang, Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Reducing Dynamic and Leakage Energy in VLIW Architectures. To appear in ACM Transactions on Embedded Computing Systems.
  • S. Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Energy-Efficient Java Execution using Local Memory and Object Co-location. IEE Proceedings - Computers and Digital Techniques.Vol. 151, No. 1, pp. 33 - 42, January 2004.
  • A. Parikh, S. Kim, M. Kandemir, N. Vijaykrishnan and M. J. Irwin. Instruction Scheduling for Low Power. Journal of VLSI Signal Processing. Vol. 37, Issue 1, pp. 129 - 149, May 2004.
  • J. Juran, A. Hurson, N. Vijaykrishnan and S. Kim. Data Organization and Retrieval on Parallel Air Channels. ACM/Kluwer Wireless Networks (WINET). Vol 10, Issue 2, pp. 183 - 195, March 2004.

    Conferences

  • S. Sundar, S. Kanth, V. Chandrasekhar, S. Srinivasan, N. Vijaykrishnan and V. Kamakoti. A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs. The 2004 International Conference on Field Programmable Technology, Dec 2004.
  • B. Kang, N. Vijaykrishnan and M. J. Irwin. Analyzing Software Influences on Substrate Noise: An ADC Perspective. International Conference on Computer Aided Design (ICCAD'04), November 2004
  • . Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, and M. J. Irwin. Improving soft-error tolerance of FPGA configuration bits. International Conference on Computer Aided Design (ICCAD'04), November 2004
  • G. Chen, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Field-level analysis for heap space optimization in embedded Java. International Symposium on Memory Management (ISMM'04), October 2004.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and R. Radhakrishnan. Inverse Discrete Cosine Transform Architecture exploiting Sparseness and Symmetry Properties. IEEE International Signal processing Workshop, Oct 2004.
  • W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M. J. Irwin, Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. IEEE 22nd International Conference on Computer Design (ICCD 2004), Oct. 2004.
  • Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Reliability-aware cosynthesis for embedded systems. IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'04), September 2004.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Analyzing object error behavior in embedded JVM environments. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04), September 2004.
  • B. Kang, N. Vijaykrishnan, M. J. Irwin and T. Theocharides. Power-Efficient Implementation of Turbo Decoder in SDR System IEEE International SoC Conference. Sept 2004.
  • T. Theocharides, G. M. Link, N. Vijaykrishnan, M. J. Irwin and V. Srikantam. A Generic Reconfigurable Neural Network Architecture Implemented as a Network on Chip. IEEE International SoC Conference. Sept 2004.
  • Y-F. Tsai, A. Hegde, N. Vijaykrishnan, and M. J. Irwin. ChipPower : An Architecture-Level Leakage Simulator. IEEE International SoC Conference. Sept 2004.
  • A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J.Irwin and T. Tuan. A Dual Vdd Low Power FPGA Architecture. International conference on Field-Programmable Logic and its Applications (FPL), Aug-Sept 2004.
    V. Degalahal, N Vijaykrishnan, M J Irwin, S. Cetiner, F. Alim, and K. Unlu. Soft Errors: Simulation and Estimation Engine. Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD'04). September 2004.
  • R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, and K. Bernstein. Soft Errors in Adder Circuits. Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD'04). September 2004.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin Analyzing object error behavior in embedded JVM environments. Proc. the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04). September 2004.
  • L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, M. J. Irwin Soft Error and Energy Consumption Interactions: A Data Cache Perspective. 2004 ACM/IEEE International Symposium on Low Power Electronics and Design, August 2004.
  • W-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing. 2004 ACM/IEEE International Symposium on Low Power Electronics and Design, August 2004.
  • H. Saputra, G. Chen, R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Code protection for resource-constrained embedded devices. ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, June 2004.
  • S. Yang, W. Wolf and N. Vijaykrishnan. Search Speed and Power Driven Integrated Software and Hardware Optimizations for Motion Estimation Algorithms Proceeding of International Conference on Multimedia and Expo, June 2004.
  • Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M.J. Irwin, "Impact of process scaling on the efficacy of leakage reduction scheme", In the Proceedings of International Conference on IC Design and Technology, May 2004
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, "Efficient VLSI Implementation of Inverse Discrete Cosine Transform", In the Proceedings of International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Montreal, Canada, May 2004.
  • W. Xu, N. Vijaykrishnan, Y. Xie, M. J. Irwin, Design of a Nanosensor Array Architecture, IEEE Great Lakes Symposium on VLSI, April 2004.
  • E. Swankowski, R. Brooks, N. Vijaykrishnan, M. Kandemir and M.J Irwin. A Parallel Architecture for Secure FPGA Symmetric Encryption. Proc. of 11th Reconfigurable Architectures Workshop, April 2004.
  • E. Lattanzi, A. Bogliolo, A. Gayasen, M. Kandemir, N. Vijaykrishnan and L. Benini. Improving Java Performance by Dynamic Method Migration on FPGAs. Proc. of 11th Reconfigurable Architectures Workshop, April 2004.
  • V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin. The effect of threshold voltages on the soft error rate. Proc. of International Symposium on Quality in Electronic Design (ISQED), March 2004.
  • M. Pirretti, G. Link, R. R. Brooks, N. Vijaykrishnan, M.Kandemir, M. J. Irwin. Fault Tolerant Algorithms for Network-On-ChipInterconnect. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Feb 2004.
  • T. . Theocharides, G. Link, E. Swankoski, N. Vijaykrishnan,M. J. Irwin, H.Schmit. Evaluating Alternative Implementations for LDPCDecoder Check Node Function. Proceedings of IEEE Computer Society Annual Symposium on VLSI, Feb 2004.
  • A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan. Reducing leakage energy in FPGAs using region-constrained placement. Proc. Twelfth ACM International Symposium on Field-Programmable Gate Arrays (FPGA'04), Feb 2004.
  • L. Li, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "A Crosstalk Aware Interconnect with Variable Cycle Transmission", Conference on Design, Automation, and Test in Europe (DATE'04), February, 2004.
  • J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, and M. J. Irwin. Scheduling Reusable Instructions for Power Reduction. Conference on Design, Automation and Test in Europe (DATE'04), Paris, France, February 16-20, 2004.
  • J. S. Hu, N. Vijaykrishnan, and M. J. Irwin. Exploring Wakeup-Free Instruction Scheduling. Proc. of the International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, February 14-18, 2004.
  • T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin and W. Wolf, Embedded Hardware Face Detection. Proc. of International Conference on VLSI Design, Jan 2004.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin, W. Wolf. An Architecture for Motion Estimation in the Transform Domain. Proc. of International Conference on VLSI Design, Jan 2004.
  • M. Derenzo, M. J. Irwin and N. Vijaykrishnan. Leakage Aware Multiplier Design. Proc. of International Conference on VLSI Design, Jan 2004.

    2003

    Journals/Magazines

  • N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and N. Vijaykrishnan. Leakage - The Next Challenge in Low Power Computing. IEEE Computer Special Issue on Power- and Temperature-Aware Computing, December, 2003.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and R. Brooks. Masking the Energy behavior of Encryption Algorithms IEE Proceedings: Computers and Digital Techniques (Invited among best papers at DATE 2003)
  • M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh. A Compiler Based Approach for Dynamically Managing Scratch-Pad Memories in Embedded Systems. IEEE Transactions on CAD
  • L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivasubramaniam Managing Leakage Energy in Cache Hierarchies. Journal of Instruction Level Parallelism, Volume 5, 2003.
  • S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam and M. J. Irwin. Partitioned Instruction Cache Architecture For Energy Efficiency. ACM Transactions on Embedded Computer Systems.

    Book Chapters

  • N. Vijaykrishnan, M. J. Irwin, M. Kandemir, L. Li and G. Chen. Designing Energy Aware Sensor Systems. To appear in Frontiers of Distributed Sensor Networks (Ed: R. R. Brooks and S. S. Iyengar), CRC Press.

    Conferences

  • S. Yang, W. Wolf and N. Vijaykrishnan. Power Modeling of VLSI motion Estination Architecture. Proceedings of the 5th Workshop on Media and Streaming Processors (MSP) held in conjunction with MICRO-6, San Deigo, CA, Dec 2003.
  • N. Vijaykrishnan. Designing Energy-Efficient and Reliable Hardware. IFIP International Conference on VLSI, Darmstadt, Germany, Dec 1-3, 2003.
  • L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Adaptive Error Protection for Energy Efficiency. International Conference on Computer Aided Design, Nov 2003.
  • R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J. Irwin and D. Duarte. Analysis of Soft-Error Rate for Flip-Flops and Scannable Latches. 2003 IEEE International SOC Conference, Sept 2003.
  • B. Kang, N. Vijaykrishnan, M. J. Irwin and D. Duarte. Substrate Noise Detector for Noise Tolerant Mixed-Signal IC 2003 IEEE International SOC Conference, Sept 2003.
  • G. Chen, G. Chen, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Energy-aware code cache management for memory-constrained Java devices. In Proc. IEEE International SOC Conference (ASIC/SOC'03), Sept 2003.
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli. An Efficient Implementation of Hierarchical Image Coding. IEEE Workshop on Signal Processing Systems, Aug 2003.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and R. Brooks. Exploiting Value Locality for Secure Energy Aware Communication. IEEE Workshop on Signal Processing Systems, Aug 2003.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, B. Mathiske, and M. Wolczko. Heap compression for memory-constrained Java environments. Proc. 18th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'03), Anaheim, California, October, 2003.
  • L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and I. Kadayif. CCC: crossbar connected caches for reducing energy. Proc. Euro-MICRO Symposium on Digital System Design, Architectures, Methods and Tools (DSD'03), Antalya, Turkey, September, 2003.
  • J. Hu, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Exploiting program hotspots and code sequentiality for instruction cache leakage management. Proc. the International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
  • E. J. Kim, K. H. Yum, G. Link, C. R. Das, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Energy optimization techniques in cluster interconnects. Proc. the International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
  • S. Kim, N. Vijaykrishnan, M. J. Irwin, and L. K. John, On Load Latency in Low-Power Caches. Proc. the International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, and M. J. Irwin. Estimating influence of data layout optimizations on SDRAM energy consumption. Proc. the International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003.
  • A. Bhatkar, R. Chandramouli, N. Vijaykrishnan and M. J. Irwin. Computation and Transmission Energy Modeling Through Profiling For MPEG4 Video Transmission. IEEE International Conference on Multimedia & Expo, 2003.
  • Y-F. Tsai, D. Duarte, N. Vijaykrishnan and M. J. Irwin. Implications of Technology Scaling on Leakage Reduction Techniques. Design Automation Conference, 2003.
  • H. Schmit, T. Kroll, M. Khusid, I. Kourtev, N. Vijaykrishnan, D. Landis The Sandbox Design Experience Course. International Conference on Microsystem Education, 2003.
  • G.Chen, B.Kang, M.Kandemir, N.Vijaykrishnan, M.J.Irwin and R.Chandramouli. Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. IPDPS 2003.
  • Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. IPDPS 2003.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, and W. Zhang. Masking the energy behavior of DES encryption, In Proc. the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March 2003.
  • W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and V. De. Compiler support for reducing leakage energy consumption. In Proc. the 6th Design Automation and Test in Europe Conference (DATE'03), Munich, Germany, March 2003.
  • S. Gurumurthi, J. Zhang, A. Sivasubramaniam, M. Kandemir, H. Franke, N. Vijaykrishnan, and M. J. Irwin. Interplay of energy and performance for disk arrays running transaction processing workloads, In Proc. the International Symposium on Performance Analysis of Systems and Software (ISPASS'03), March 2003.
  • J. S. Hu, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir. Using dynamic branch behavior for power-efficient instruction fetch, In Proc. IEEE CS Annual Symposium on VLSI (ISVLSI'03), Tampa, Florida, February 2003.
  • V. Degalahal, N. Vijaykrishnan and M. J. Irwin. Analyzing Soft Errors in Leakage Optimized SRAM Designs. Proc. of International Conference on VLSI Design, Jan 2003.

    2002

    Books

  • Java Microarchitectures. Editors N. Vijaykrishnan and M. Wolczko. Kluwer Academic. April 2002.

    Journals

  • G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and M. Wolczko. Influence of garbage collection on memory system energy. ACM Transactions on Embedded Computer Systems (TECS).
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf. Using memory Compression for Energy Reduction in an Embedded Java System. Journal of Circuits, Systems and Computers.
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI. (BEST TRANSACTIONS ON VLSI PAPER AWARD)
  • N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Kim, W. Ye and D. Duarte. Evaluating Integrated Hardware-Software Optimizations using a Unified Energy Estimation Framework. IEEE Transactions on Computers.
  • N. An, S. Gurumurthi, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Energy-Performance Trade-offs for Spatial Access Methods on Memory-Resident Data. International Journal on Very Large Databases.

    Book Chapters

  • M. Kandemir, N. Vijaykrishnan and M. J. Irwin. Compiler Optimizations for Low Power Systems. In Power-Aware Computing, Kluwer Academic. Editors R. Melhem and R. Graybill. 2002.
  • N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam and M. J. Irwin. Tools and Techniques for Integrated Hardware-Software Energy Optimizations. In Low Power Design Methodologies. Editors Jan M. Rabaey and Massoud Pedram. Kluwer Academic.

    Conferences

  • W. Zhang, J. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-directed instruction cache leakage optimization. In Proc. the 35th Annual International Symposium on Microarchitecture (MICRO-35), Istanbul, Turkey, November 2002.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. PennBench: a benchmark suite for embedded Java. In Proc. the 5th Annual IEEE Workshop on Workload Characterization (WWC'02), Austin, TX, November 2002.
  • T. Li, L. K. John, A. Sivasubramaniam, N. Vijaykrishnan, J. Rubio. Understanding and Improving Operating System Effects in Control Flow Transfer. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002.
  • D. Charles, A. Hurson and N. Vijaykrishnan. Improving ILP with instruction-reuse cache hierarchy. In Proc. of 5th International Conference on Algorithms and Architectures for Parallel Processing, Beijing, 23-25 October 2002.
  • L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivasubramaniam. Leakage Energy Management in Cache Hierarchies. The Eleventh International Conference on Parallel Architectures and Compilation Techniques. Charlottesville, Virginia, September 22-25, 2002.
  • J. Zhao, R. Chandramouli, N. Vijaykrishnan, M. J. Irwin, B. Kang, and S. Somasundaram* Influence of MPEG-4 Parameters on System Energy. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin. Scaling of the Effectiveness of Power Reduction Schemes and the Impact of Temperature Management. In Proc. of International Conference on Computer Design, Freiburg, Germany September 16-18, 2002.
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Predictive precharging for bitline leakage energy reduction. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin. Impact of Technology Scaling and Packaging on Dynamic Voltage Scaling Techniques. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • R. Ramanarayanan, N. Vijaykrishnan and M. J. Irwin. Characterizing Dynamic and Leakage Power Behavior in Flip-Flops. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • G. Essakimuthu, N. Vijaykrishnan and M. J. Irwin. An Analytical Power Estimation Model For Crossbar Interconnects. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • Y-F. Tsai, N. Vijaykrishnan and M. J. Irwin. A Sizing Model for SRAM Data Preserving Sleep Transistors. IEEE International ASIC/SOC Conference, Sept 25-28 2002.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko. Adaptive Garbage Collection for Battery-Operated Environments. 2nd USENIX Java[tm] Virtual Machine Research and Technology Symposium, August 1-2, 2002.
  • H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. Hu, C-H.Hsu, and U. Kremer. Energy-conscious compilation based on voltage scaling. In Proc. ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), Berlin , Germany , June 19-21, 2002.
  • J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, and W. Zhang. Compiler-directed cache polymorphism. Proc. ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), Berlin , Germany , June 19-21, 2002.
  • V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Scheduler-based DRAM energy management. In Proc. Design Automation Conference (DAC'02), New Orleans, LA, June 2002.
  • B. Kang, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli. Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter. International Conference on Acoustics, Speech and Signal Processing (ICASSP). Orlando, Florida, May 13 - 17, 2002
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf. Energy Savings Through Compression in Embedded Java Environments. Tenth International Symposium on Hardware/Software Codesign, Colorado, May 6-8, 2002
  • D. Duarte, N. Vijaykrishnan, and M. J. Irwin. Impact of Technolgoy Scaling on the Clock System Power. IEEE Computer Society, Annual Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, USA, April 2002.
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Hardware-software co-adaptation for data-intensove embedded applications IEEE Computer Society, Annual Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, USA, April 2002.
  • I. Kadayif, N. Orr, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Instruction selection/scheduling using an energy-aware instruction set architecture, In Proc. the 6th Workshop on Languages, Compilers, and Runtime Systems for Scalable Computers (LCR'02), Washington D.C., March 2002.
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin. A Complete Phase-Locked Loop Power Consumption Model. In Proc. the 5th Design Automation and Test in Europe Conference (DATE'02), Paris, France, 4-8 March, 2002.
  • J. Hu, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Power-efficient trace caches. In Proc. the 5th Design Automation and Test in Europe Conference (DATE'02), Paris, France, 4-8 March, 2002.
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and A Sivasubramaniam. EAC: a compiler framework for high-level energy estimation and optimization. In Proc. the 5th Design Automation and Test in Europe Conference (DATE'02), Paris, France, 4-8 March, 2002.
  • G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and M. Wolczko. Tuning garbage collection in an embedded Java environment, In Proc. the 8th International Symposium on High-Performance Computer Architecture (HPCA'02), Cambridge, MA, February 2-6, 2002.
  • S. Gurumurthi, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, T. Li, and L. K. John. Using complete machine simulation for software power estimation: the SoftWatt approach. In Proc. the 8th International Symposium on High-Performance Computer Architecture (HPCA'02), Cambridge, MA, February 2-6, 2002.
  • V. Delaluz, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam, and I. Kolcu. Compiler-directed array interleaving for reducing energy in multi-bank memories. In Proc. 7th Asia and South Pasific Design Automation Conference & 15th International Conference on VLSI Design (VLSI Design / ASPDAC '02), January 7-11, 2002, Banglore, India.
  • D. Duarte, Y-T. Fai, N. Vijaykrishnan, M. J. Irwin. Evaluating Run-Time Techniques for Leakage Power Reduction. In Proc. 7th Asia and South Pasific Design Automation Conference & 15th International Conference on VLSI Design (VLSI Design / ASPDAC '02), January 7-11, 2002, Banglore, India.

    2001

    Journals

  • V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin, "Hardware and Software techniques for Controlling DRAM Power Modes" IEEE Transactions on Computers, Dec 2001.
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Ye, "Influence of Compiler Optimizations on System Power" IEEE Transactions on VLSI Systems .
  • B.Bishop, V.Lyuboslavasky, N. Vijaykrishnan and M. J. Irwin, "Design Considerations for Databus Charge Recovery" IEEE Transactions on VLSI Systems, 9(1), pp. 104-106, Feb 2001.
  • R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Sabarinathan, and J. Rubio ``Java Runtime Systems: Characterization and Architectural Implications'', IEEE Transactions on Computers, Feb 2001.
  • G. Esakkimuthu, H.S. Kim, M. Kandemir, N. Vijaykrishnan, and M.J.Irwin, "Investigating Memory System Energy Behavior using Software and Hardware Optimizations", VLSI Design Journal, 12(2), pp. 151-165, Feb 2001.

    Book Chapters

  • H. S. Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Characterization of memory energy behavior, Book Chapter in Workload Characterization of emerging Computer Applications, Kluwer Academic, 2001.
  • T. Li, L. John, N. Vijaykrishnan and A. Sivasubramaniam. Characterizing Operating System Activity in SPECjvm98 benchmarks. Book Chapter in Workload Characterization of emerging Computer Applications, pp. 165-180, Kluwer Academic, 2001.

    Conferences

  • W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte and Y. Tsai. Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction. The 34th Annual International Symposium on Microarchitecture, Austin, December 2001.
  • N. Kirubanandan, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Memory energy characterization and optimization for the SPEC2000 benchmarks. Proc. the 4th IEEE Annual Workshop on Workload Characterization (WWC'01), Austin, Texas, December 2, 2001.
  • S. Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Energy-efficient instruction cache using page-based placement. In Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'01), Atlanta, GA, November 2001.
  • J. Hezavei, N. Vijaykrishnan, M. J. Irwin and M. Kandemir, Input sensitive high-level power analysis, The 2001 IEEE Workshop on signal processing systems, Antwerp, Belgium, September 26-28, 2001.
  • H. Y. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. A Framework for Exploring Energy-Efficient VLIW Architectures. International Conference on Computer Design, Sept 2001.
  • S. Tomar, S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Use of local memory for efficient Java execution. International Conference on Computer Design, Sept 2001.
  • G. Thirugnanam, N. Vijaykrishnan and M. J. Irwin. A Novel Low Power CAM Design. International ASIC/SOC Conference, Sept 2001.
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin and M. Kandemir. Evaluating the Impact of Architectural-Level Optimizations on Clock Power. International ASIC/SOC Conference, Sept 2001.
  • N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and S. Gurumurti, "Analyzing Energy Behavior of Spatial Access Methods for Memory-Resident Data" International Conference on Very Large Databases, Sept. 2001.
  • S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin and E. Geethanjali. Exploring Partitioned Cache Organizations for Energy Efficiency. International Symposium on Low Power Design and Electronics, August 2001
  • I. Kadayif, T. Chinoda, M. Kandemir, N. Vijaykrishnan, M.J. Irwin, and A. Sivasubramaniam vEC: Virtual Energy Counters. ACM SIGPLAN/SIGSOFT Workshop on Program Analysis for Software Tools and Engineering June 2001.
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. Ramanujam Morphable Cache Architectures: Potential Benefits In Proc. of Languages, Compilers, and Tools for Embedded Systems: ACM SIGPLAN Workshop, June 2001
  • A. Parikh, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and I. Kadayif. Energy-Conscious Instruction Scheduling for VLIW Architectures. 9th Workshop on Compilers for Parallel Computers, June 27-29, Edinburgh, Scotland, UK
  • Dynamic management of scratch-pad memory space, by M. Kandemir, J. Ramanujam, M. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. In Proc. 38th Design Automation Conference (DAC'01), Las Vegas, NV, June 2001.
  • P. Khosla, H. Schmit, M. J. Irwin, N. Vijaykrishnan, T. Cain, S. Levitan, D. Landis. SoC Design Skills: Collaboration Builds Stronger SoC Design Team, International Conference on Microsystem Education, June 2001
  • A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, "VLIW Scheduling for Energy and Performance", In Proc. IEEE CS Annual Workshop on VLSI, April 2001.
  • N. Vijaykrishnan, M. Kandemir, S. Tomar, S. Kim, A. Sivasubramaniam and M. J. Irwin Energy Characterization of Java Applications from a Memory Perspective, Java Virtual Machine Research and Technology Symposium, April 2001.
  • R. Athavale, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, Influence of Array Allocation Mechanisms on Memory System Energy, International Parallel and Distributed Processing Symposium, April 2001.
  • S. Tomar, N. Vijaykrishnan, M. Kandemir, R. Shetty, M. J. Irwin "Energy Optimization Using Object Co-Location in Java", JOSES: Java Optimization Strategies for Embedded Systems Workshop in conjunction with ETAPS 2001, April 2001.
  • V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, DRAM Energy Management Using Software and Hardware Directed Power Mode Control, 7th International Conference on High Performance Computer Architecture, Jan 2001.
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin and M. Kandemir, Formulation and Validation of an Energy Dissipation Model for Clock Generation Circuitry and Distribution Network, 14th International Conference on VLSI Design, Jan 2001.

    2000

    Journals

  • N. Vijaykrishnan and N. Ranganathan, Object addressing support for a Java processor, IEE Proceedings - Computers and Digital Techniques, Nov. 2000.

    Conferences

  • A. James, A. R. Hurson, N. Vijaykrishnan and Boonsiriwattanakul, "Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues", International Conference on High Performance Computing, December 2000.
  • A. Parikh, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin, "Energy-Aware Instruction Scheduling", International Conference on High Performance Computing, December 2000.
  • V. Delaluz, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin, "Energy-Oriented Compiler Optimizations for Partitioned Memory Architectures", International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, November 2000.
  • H. S. Kim, M. J. Irwin, N. Vijaykrishnan and M. Kandemir, "Effect of Compiler Optimatizations on Memory Energy", Proc. of Workshop on Signal Processing System, October 2000
  • M. J. Irwin, M. Kandemir, N. Vijaykrishnan and A. Sivasubramaniam, "A Holistic Approach to System Level Energy Optimization", International Workshop on Power and Timing Modeling, Optimization and Simulation, Sept 2000.
  • V. Lyuboslavsky, B. Bishop, N. Vijaykrishnan and M. J. Irwin, "Design of Databus Charge-Recovery Mechanism", Thirteenth Annual International ASIC/SOC Conference, pp. 283-287, Sept 2000.
  • D. Duarte, M. J. Irwin and N. Vijaykrishnan, "Modeling Energy of the Clock Generation and Distribution Circuitry", Thirteenth Annual International ASIC/SOC Conference, pp. 261-265, Sept 2000.
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin, W. Ye, and I. Demirkiran, Register Relabeling: A Post Compilation Technique for Energy Reduction, Workshop on Compilers and Operating Systems for Low Power, Sept 2000.
  • R. Athavale, N. Vijaykrishnan and M. Kandemir, 'Annotation Based Energy Optimization Using Array Interleaving', Second Annual Workshop on Hardware Support for Objects and Microarchitectures for Java, pp. 16-20, Austin, Sept 2000.
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and H. Y. Kim, "Experimental Evaluation of Energy Behavior of Iteration Space Tiling", International Workshop on Languages and Compilers for Parallel Computing, August 2000.
  • E. Geethanjali, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Memory System Energy: Influence of Hardware-Software Optimizations", International Symposium on Low Power Design and Electronics, July 2000.
  • N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Y. Kim and W. Ye, "Energy-driven integrated hardware-software optimizations using SimplePower" In Proc. the International Symposium on Computer Architecture, June 2000.
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and H. Y. Kim, "Towards Energy-Aware Iteration Space Tiling", In Proc. of Languages, Compilers, and Tools for Embedded Systems : ACM SIGPLAN Workshop , pp. 108, June 18, 2000.
  • W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of SimplePower: a cycle-accurate energy estimation tool", In Proc. the 37th Design Automation Conference (DAC'00), Los Angeles, California USA, June 5-9, 2000.
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye, "Influence of compiler optimizations on system power", In Proc. the 37th Design Automation Conference (DAC'00), Los Angeles, California USA, June 5-9, 2000.
  • T. Li, L. K. John, N. Vijaykrishnan, A. Sivasubramaniam, A. Murthy and J. Sabarinathan, `Using Complete System Simulation to Characterize SPECjvm98 Benchmarks', Proc. of International Conference on Supercomputing, Santa Fe, May 8-11, 2000.
  • H. Y. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, "Multiple Access Caches: Energy Implications", In Proc. IEEE CS Annual Workshop on VLSI, pp. 37-42, April 27-28, 2000, Orlando, FL
  • A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, "Instruction Scheduling Based on Energy and Performance Constraints", In Proc. IEEE CS Annual Workshop on VLSI, pp. 53-58, April 27-28, 2000, Orlando , FL
  • J. Hezavei, N. Vijaykrishnan and M. J. Irwin, "A Comparative Study of Power Efficient SRAM Designs", Great Lakes Symposium on VLSI, March, 2000.
  • R. Radhakrishnan, N. Vijaykrishnan, L. K. John and A. Sivasubramaniam, 'Architectural Issues in Java Run-time Systems', International Conference on High Performance Computer Architecture, pages 387-398, Jan 2000.

    1999

    Conferences

  • M. J. Irwin and N. Vijaykrishnan, " Energy Issues in Multimedia Systems", Proc. of Workshop on Signal Processing System, pp. 24-33, Taipei, Taiwan, October 1999.
  • R. Y. Chen, N. Vijaykrishnan, and M. J. Irwin, 'Clock Power Issues in System-on-Chip designs' Proc. of IEEE CS VLSI'99 Workshop, pp.48-53, April 1999.
  • V. Krishna, N. Ranganathan and N. Vijaykrishnan, 'Efficient Energy Reduction Using Dynamic Frequency Clocking and Multiple Voltages', The Twelfth International Conference on VLSI Design, pp. 440-445, Jan 1999.
  • S. Boonsiriwattanakul, A. R. Hurson, N. Vijaykrishnan and C. Chehadeh, "Energy-Efficient Indexing on Parallel Air Channels in a Mobile Database Access System" Proc. of The Fifth Intl' Conference of the Information Systems Analysis and Synthesis, 4:30-38, July31-August 4, 1999.
  • A. Murthy, N. Vijaykrishnan and A. Sivasubramaniam, 'How can hardware support Just-in-Time Compilation ?', Workshop on Hardware Support for Objects amd Microarchitectures for Java, pp. 15-19, October 10, 1999.
  • N. Vijaykrishnan and N. Ranganathan, 'Tuning branch predictors to support Java method invocation' Proc. of USENIX COOTS'99, pp.217-228, May 1999.

    1998

    Journals

  • N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, 'A Linear Array Processor with Dynamic frequency Clocking for Image Processing Applications', IEEE Transactions on Circuits and Systems for Video Technology, August 1998, Volume 08, Number 04, pp. 435-445.
  • R. Chandramouli, N. Vijaykrishnan and N. Ranganathan, 'Sequential Tests for Integrated Circuit Failure Analysis', IEEE Transactions on Reliability, December 1998.

    Conferences

  • N. Vijaykrishnan and N. Ranganathan, 'Object Addressing Support for a Java Processor', The Sixth International Conference on Advanced Computing, pp. 61-67 December 1998.
  • V. Krishna, N. Ranganathan and N. Vijaykrishnan, 'An Energy Efficient Scheduling Scheme for Signal Processing Applications', Thirty Second Asilomar Conference on Signals, Systems and Computers, November 1998, pp. 1057-1061.
  • R Chandramouli, N Vijaykrishnan, N Ranganathan, 'SPRT for Weibull Distributed Integrated Circuit Failures', Proceedings of SPIE on Microelectronic Manufacturing, pp. 147-158, September 1998.
  • N. Vijaykrishnan, 'Issues in the Design of a Java Processor Architecture', Ph.D. Dissertation, University of South Florida, July 1998.
  • N. Vijaykrishnan, N. Ranganathan and R. Gadekarla, 'Object-Oriented Architectural Support for a Java Processor', Lecture Notes in Computer Science 1445, pp. 330-354, Proceedings of ECOOP'98, the 12th European Conference on Object-Oriented Programming, July 1998.
  • R Chandramouli, N Vijaykrishnan, N Ranganathan, 'Burn-in Evaluation for VLSI Devices based on SPRT', International Conference in Reliability and Survival Analysis, Illinois, USA, May 1998

    Before 1998

  • N. Vijaykrishnan, N. Ranganathan and N. Bhavanishankar, 'DFLAP: Dynamic Frequency Linear Array Processor', International Conference on Image Processing, Switzerland, Vol 2, 1996, pp. 1007-1010.
  • N. Ranganathan, N. Vijaykrishnan and N. Bhavanishankar, 'A VLSI Array Architecture with dynamic clocking', International Conference on Computer Design, Austin, Texas, pp. 137-140, 1996.
  • N. Vijaykrishnan, R. Chandramouli and N. Ranganathan, 'Functional Reconfiguration for Fault Tolerance: A New Approach', International Conference on Modelling, Simulation and Optimization, Australia, 1996.
  • N. Vijaykrishnan and N. Ranganathan, 'SUBGEN: A Genetic Approach for Subcircuit Extraction', Proceedings of Ninth International Conference on VLSI Design, 1996, pp. 343-345.
  • N. Venkateswaran, S.Pattabiraman, V. Srinivasan, N. Vijaykrishnan and S. Balamurugan, 'A Unified Approach to VLSI layout Automation and Algorithm Mapping on processor arrays', Proceedings V NASA VLSI Conference, 1993, pp. 11.5.1 - 11.5.16.

    Articles

  • M. J. Irwin, M. Kandemir, and N. Vijaykrishnan. SimplePower: A cycle-accurate energy simulator. IEEE TCCA Newsletter
  • M. J. Irwin and N. Vijaykrishnan, A Transition Sensitive, Architectural Level Power Analysis Approach, IEEE CS TCVLSI Newsletter, pp. 6-11, Summer 1999.
  • N.Vijaykrishnan, "Java Technology-Based Microprocessors: The Past, The Future", Pioneers' Progress with picoJavaTM Technology, Sun Microsystems, Volume 3, Spring 1999.
  • N. Vijaykrishnan, 'Future Technologies and Architectures', looking .forward, Vol 5, No 1, 1997.
  • N. Vijaykrishnan, 'Studying Abroad', looking .forward, IEEE Computer Society student newsletter, Vol 2 No 3, 1994.