2008-Present Journal Articles
Nanodevice and architectures
1. Mookerjea, S., R. Krishnan, S. Datta and V. Narayanan. Effect of Enhanced Miller Capacitance on Large Signal Switching of Inter-Band Tunnel Transistors. To appear IEEE Electron Device Letters (EDL).
2. Mookerjea, S., R. Krishnan, S. Datta and V. Narayanan. September 2009. Effective Output Capacitance and Drive Current for Tunnel-FET (TFET) CV/I Estimation. IEEE Transactions on Electron Devices (TED). 56(4):2092-2098.
3. Eachempati, S., N. Vijaykrishnan, A. Nieuwoudt, Y. Massoud. April 2009. Predicting the Performance and Reliability of Future Field Programmable Gate Arrays Routing Architectures with Carbon Nanotube Bundle Interconnect. IET Circuits, Devices, & Systems 3(2):64-75. (First author supervised by candidate)
Reconfigurable Computing
4. Kim, J., P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms using Algorithmic/Architectural Optimization. To appear in IEEE Transactions on Computers
5. Gayasen, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. July 2008. Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Transactions on VLSI 16(7):882-893. (First author co-supervised by candidate)
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On-Chip Networks
6. Nicopoulos, C. A., S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. On the Effects of Process Variation in Network-on-Chip Architectures. To appear in IEEE Transactions on Dependable and Secure Computing (TDSC). (First two authors supervised by candidate)
7. Srinivasan, S., F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2008. Exploring Architectural Solutions for Energy Optimizations in Bus Based SoC. IET Computers & Digital Techniques 2(5):347-354.
Reliability
8. Ramanarayanan, R., V. Degalahal, R. Krishnan, J. S. Kim, V. Narayanan, Y. Xie, M. J. Irwin & K. Unlu. July-September 2009. Modeling Soft Errors at Logic and Device Level. IEEE Transactions on Dependable and Secure Computing (TDSC) 6(3):202-216.
9. Debole, M., R. Krishnan, W. Wang, V. Balakrishnan, Y. Cao, Y. Wang, L. Hong, Y. Xie & V. Narayanan. August 2009. New-Age: A Negative Bias Temperature Instability Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming (IJPP). 37(4):417-431.
10. Mutyam, M., F. Wang, K. Ramakrishnan, N. Vijaykrishnan, M. Kandemir, Y. Xie & M. J. Irwin. July 2009 Process Variation Aware Adaptive Cache Architecture and Management. IEEE Transactions on Computers (TC). 58(7):865-877.
11. Hu, J., F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. July 2009. Compiler-Directed Instruction Duplication for Soft Error Detection in Embedded Systems. ACM Transactions on Embedded Computing Systems 8(4)27:1-27:29.
12. Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. 2009. Total Power Optimization for Combinational Logic Using Genetic Algorithms. To appear in Journal of VLSI Signal Processing Systems.
13. Ragheb, T., A. Ricketts, M. Modal, S. Kirolos, G. Link, N. Vijaykrishnan, Y. Massoud. February 2009. Design of Thermally Robust Clock Trees using Dynamically Adaptive Clock Buffers. IEEE Transactions on Circuits and Systems (TCAS) 56(2):374-383. (Second and fifth authors supervised by candidate)
14. Yang, S., W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, Y. Xie. July 2008. Case Study of Reliability-Aware and Low-Power Design. IEEE Transactions on Very Large Scale Integration (VLSI) 16(7):861-873.
15. Srinivasan, S., R. Krishnan, P. Mangalagiri, Y. Xie, N. Vijaykrishnan, M. J. Irwin, K. Sarpatwari. April-June 2008. Toward Increasing FPGA Lifetime. IEEE Transactions on Dependable and Secure Computing 5(2):115-127. (Third three authors supervised by candidate)
16. Celik, C., K. Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M. J. Irwin, Y. Xie. August 2008. Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear Chemistry 278(2):509-512. (Third author supervised and fourth author co-supervised by candidate)
Computer Architecture
17. Tsai, Y., F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. April 2008. Design Space Exploration for Three-Dimensional Cache. IEEE Transactions on VLSI 16(4):444-455. (First author supervised by candidate)