POSTER SESSION

A Novel Technique for Noise-Tolerance in Dynamic Circuits

S. Goel, T. Darwish, M. Bayoumi – University of Louisiana at Lafayette

Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code Using Alternative Coding

X. Shang, B. Oelmann – Mid Sweden University, Sweden

The Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder

H. Lee – University of Connecticut

A Fast Architectural Leakage Power Simulator for VHDL Structural Descriptions

C. Gopalakrishnan, S. Katkoori – University of South Florida

Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association

M-J. Seow, H. Ngo, V.K. Asari - Old Dominion University

Pre-computation of Rotation Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations

S. Ravichandran, V.K. Asari – Old Dominion University

Self-Timed Design with Dynamic Domino Circuits

J-L. Yang, E. Brunvand – University of Utah

Hardwae-only Compression to Reduce Cost and Improve Utilization of Address Buses

J. Liu, N.R. Mahapatra, K. Sundaresan – State University of New York

Automated Dynamic Memory Data Type Implementation Exploration and Optimization

M. Leeman, C. Ykman, V.De Florio, G.De Coninck – K.U. Leuven and IMEC, Belgium

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects

P. Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars ''J'' Svensson – Chalmers University of Technology, Sweden

Decoder-Based Multi-Context Interconnect Architecture

A. Lodi, L. Ciccarelli, A. Cappelli, F. Campi, M. Toma – University of Bologna, Italy

Titan II : An IPComp Processor for 10Gbit/sec networks

I. Papaefstathiou – Hellas Foundation of Research and Technology, Greece

Frequency Domain Approach for CMOS Ultra-Wideband Radios

H-J. Lee, D.S. Ha – Virginia Tech University

Getting High-Performance Silicon from System-Level Design

W.R. Davis – North Carolina State University

Testable Sequential Circuit Design Partitioning for Pseudoexhaustive Test

B. Shaer, K. Aurangabadkar, N. Agarwal – University of Minnesota Duluth

Joint Minimization of Power and Area Overhead in Scan Testing by Scan Cell Reordering

S. Ghosh, S. Basu, N. A. Touba – University of Texas at Austin

Hardware Implementation of Data Compression Algorithms for Memory Energy Optimization

L. Benini, D. Bruni, A. Macii, E. Macii – Universita di Bologna and Politecnico di Torino, Italy

Dynamic Coding Technique For Low-Power Data Bus

M. Madhu, V.S. Murty, V. Kamakoti – Indian Institute of Technology, India

Fast and Precise Power Prediction for Combinational Circuits

H. Li, J.K. Antonio, S.K. Dhall – University of Oklahoma

High Throughput Power-aware FIR Filter design based on fine-grain pipelining multipliers and adders

J. Di, J. S. Yuan, R. Demara – University of Central Florida

Code Compression Techniques for Embedded Systems

K. Sundaresan, N. R. Mahapatra – State University of New York

Random Characterization of Design Automation Algorithms

S.K. Kondapuram, P. M. Maurer – Baylor University

Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing

H. Tang, H. Zhang and A. Dobol – State University of New York

Equalizing Filter Design for Crosstalk Cancellation

J. Ren, M. Greenstreet – University of British Columbia, Canada

Quantum Voltage Comparator for 0.07 um CMOS Flash A/D Converters

Y. Joo, K. Choi, J. Ghaznavi – Penn State University

Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC

J. Lundgren, B. Oelmann, T. Ytterdal, P. Eriksson, M. Abdalla, M. O'Nils – Mid Sweden University and Norwegian University of Science and Technology

Enhanced Techniques for Current Balanced Logic in Mixed- Signal ICs

L. Yang and J.S. Yuan – University of Central Florida