IEEE COMPUTER SOCIETY SYMPOSIUM ON VLSI

Thursday, 20 February, 2003

Welcome and Opening of ISVLSI ’03 (8:00-8:10 am)

V. Narayanan, General Chair

A. Smailagic and N. Ranganathan, Program Chair

Emerging Trends in VLSI Systems (8:10-10:40 am)

Design Methodology Research Over the Next 10-20 Years

J. Harlow, Semiconductor Research Corporation

Future Challenges in VLSI Design

J. Fortes, University of Florida

Networks-on-Chip

R. Marculescu – Carnegie Mellon University

Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools

S. Das, A. Chandrakasan, R. Reif - MIT

Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory

S. Frost, A. Rodrigues, C. A. Giefer, P. M. Kogge – University of Notre Dame

Break (10:40-10:55 am)

Advanced VLSI Design (10:55-11:55 am)

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS

K. Das, R.B. Brown – University of Michigan

Power Comparison of Throughput Optimized IC Busses

E. Malley, A. Salinas, K. Ismail, L. Pileggi – IBM and Carnegie Mellon University

LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits

Y. Im, K. Roy – Purdue University

Lunch (11:55-12:50)

PANEL - Electronic Textiles (12:50-2:10 pm)

Panelists - Justin Harlow, SRC; Sundaresan Jayaraman, GaTech; Radu Marculescu, CMU and Sigurd Wagner, Princeton

POSTER Session (2:10-3:45 pm)

Break (3:45-4:00 pm)

VLSI Circuits and Systems (4:00-5:20 pm)

Interconnect Effort - A Unification of Repeater Insertion and Logical Effort

S. Srinivasaraghavan, W. Burleson – University of Massachusetts at Amherst

Modified Sakurai-Newton Current Model and its Applications for Digital CMOS Circuit Design

M. Mansour, Mohammad M. Mansour and A. Mehrotra – University of Illinois at Urbana-Champaign

A Fine-Grain Phased Logic CPU

R.B. Reese, M. A. Thornton, C. Traver – Mississippi State Univ., Southern Methodist Univ., and Union College

An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters

K-H. Baek, M-J. Choe, S-M. Kan - Rockwell Scientific Company and Univ. of California Santa Cruz

System-on-a-Chip Design (5:20– 6:00 pm)

Energy Benefits of a Configurable Line Size Cache for Embedded Systems

C. Zhank, F. Vahid, W. Najjar – University of California at Riverside

Reconfigurable Fast Memory Management System Design for Application Specific Processors

S.K. Agun, M. Chang – Illinois Institute of Technology and Iowa State University

Banquet Dinner (6:15-8:15 pm)

Friday, 21 February 2003

System Level Design (8:00-9:00 am)

System Design Approach To Power Aware Mobile Computers

A. Smailagic – Carnegie Mellon University

Architecture, Memory, and Interface Technology Integration of a Configurable System-on-Chip (CSoC) – J. Becker, M. Vorbach, Universitaet Karlsruhe and PACT , Germany

A Framework for Security on NoC Technologies

C.H. Gebotys, R.J. Gebotys – University of Waterloo, Canada

Low Power VLSI System Design I (9:00-10:20 am)

Peak Power Minimization Through Datapath Scheduling

S. P. Mohanty, N. Ranganathan, S. K. Chappid – University of South Florida

Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch

J. S. Hu, N. Vijaykrishnan, M.J. Irwin, M. Kandemir - Penn State University

Energy Recovering ASIC Design

C.H. Ziesler, J. Kim, M. C. Papaefthymiou – University of Michigan

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors

Y. Bai, R.I. Bahar – Brown University

Break (10:20-10:35 am)

Invited Talk - Mary Jane Irwin - Penn State (10:35-11:25 am)

Lunch (11:35-12:35)

Low Power VLSI System Design II (12:35-2:15 pm)

An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages

R. Bai, S. Kulkarni, W. Kwong, A. Srivastava, D. Sylvester, D. Blaauw – University of Michigan

Low Power Test Set Embedding Based on Phase Shifters

L. Bellos, D. Kagaris, D. Nikolos – University of Patras, Greece, and Southern Illinois University

Supply Voltage Scalable System Design Using Self-Timed Circuits

W. Kuang, J.S. Yuan, A. Ejnioui – University of Central Florida

Optimal Shielding/Spacing Metrics for Low Power Design

R. Arunachalam, E. Acar, S. Nassif – IBM

An O(N) Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.

A. U. Diril, Y. S. Dhillon, K. Choi and A. Chatterjee - Georgia Tech.

PANEL: Design and CAD issues under uncertain or faulty behavior (2:15-3:35 pm)

Panelists - Shawn Blanton, CMU; Sani Nasif, IBM; Lou Scheffer, Cadence; James Tschanz, Intel

Break (3:35-3:50 pm)

Physical Design, Synthesis and Optimization (3:50- 4:50 pm)

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization

A.B. Kahng, B. Liu – University of California at San Diego

Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies

M. A. Elgamel, K.S. Tharmalingam, M. A. Bayoumi – University of Louisiana at Lafayette

Block-wise Extraction of Rent's Exponents for an Extensible Processor

T Ahonen, T. Nurmi, J. Nurmi, J. Isoaho – Tampere University of Technology and Turku University, Finland

Closing Remarks (4:50-5:35 pm)