Downloads
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SimPower
An execution driven, cycle-accurate RTL energy estimation tool that uses transition sensitive energy models for in-order 5-stage pipelined datapath. Perfect cache is assumed for this release. The ISA of simulated machine is a subset of the instruction set (the integer part excluding division) of Simplescalar. The tool is currently not supported.
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Cerebrum
Provides a graphical framework for creating hardware designs and translating those designs to a Single- or Multi-FPGA hardware system.
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SEAT
Supports soft error analysis at device level (SEAT-DA), circuit level (SEAT-CA), logic level (SEAT-LA) and architecture level (SEAT-AA). The tool creates library of abstractions to serve as an interface between the different levels used for analysis