Curriculum
Vita
Vijaykrishnan Narayanan
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EDUCATION: |
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1993 |
B.E., Department of Computer Science
and Engineering, SVCE, University of
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1998 |
Ph.D., Department of Computer
Science and Engineering,
Thesis Advisor: N. Ranganathan Thesis Title: Issues in the Design
of a Java Processor Architecture |
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EXPERIENCE: |
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1995-98 |
Research Assistant, Center for
Microelectronics Research, |
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1996 |
Instructor, Computer Science and
Engineering, |
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1998-2003 |
Assistant Professor, Computer
Science and Engineering, The
University |
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2003-2007 |
Associate Professor, Computer
Science and Engineering, The University
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2007- |
Professor, Computer Science
and Engineering, The
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Awards for Scholarship or Professional Activity.
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Date |
Honors and Awards |
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2006 |
PSES Outstanding Research Award |
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2005 |
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2004 |
ACM ASPLOS 2004 Outstanding
Service in Organizing Tutorials Recognition |
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2004 |
ACM SIGDA 2004 Outstanding
Contributions to the Organization of ISLPED 2004 |
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2002 |
2002 IEEE Circuits and Systems
Society VLSI Transactions Best Paper Award Title: A Clock Power Model to Evaluate Impact of
Architectural and Technology Optimizations (Authors: D. |
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2002 |
IEEE Computer Society Certificate of Appreciation for
Outstanding Service to the Chapters Activities Board |
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2001 |
National Science Foundation
(NSF) CAREER Award
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2000 |
The ACM SIGDA Outstanding New
Faculty Award (Presented at DAC, consisting of a $10,000 grant and a
citation; the SIGDA Outstanding New Faculty Award recognizes a junior faculty
member early in her or his academic career who demonstrates outstanding
potential as an educator and/or researcher in the field of electronic design
automation.) |
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1998 |
IEEE Computer Society/Upsilon Pi
Epsilon Award for Academic Achievement |
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1996 |
IEEE Computer Society Richard E.
Merwin Award |
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1994-95 |
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1993 |
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1987 |
Outstanding Student of School Award |
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1. Refereed publications.
Articles published in refereed journals.
1. S. Mookerjea, R. Krishnan,
S. Datta and V. Narayanan. Effect of Enhanced Miller Capacitance on Large
Signal Switching of Inter-Band Tunnel Transistors. To appear IEEE Electron
Device Letters (EDL).
2.
Kim, J., P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan, K.
Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. An Automated Framework
for Accelerating Numerical Algorithms on Reconfigurable Platforms using
Algorithmic/Architectural Optimization. To appear in IEEE
Transactions on Computers.
3.
Nicopoulos, C. A.,
S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. On the Effects of Process Variation in
Network-on-Chip Architectures. To appear
in IEEE Transactions on
Dependable and Secure Computing (TDSC). (First two authors supervised by candidate)
4. S. Mookerjea, R. Krishnan,
S. Datta and V. Narayanan. September 2009. Effective Output Capacitance and
Drive Current for Tunnel-FET (TFET) CV/I Estimation. IEEE Transactions on
Electron Devices (TED). 56(4):2092-2098.
5. R. Ramanarayanan, V.
Degalahal, R. Krishnan, J. S. Kim, V. Narayanan, Y. Xie, M. J. Irwin & K.
Unlu. July-September 2009. Modeling Soft Errors at Logic and Device Level. IEEE
Transactions on Dependable and Secure Computing (TDSC) 6(3):202-216.
6. M. Debole, R. Krishnan, W.
Wang, V. Balakrishnan, Y. Cao, Y. Wang, L. Hong, Y. Xie & V. Narayanan. August
2009. New-Age: A Negative Bias Temperature Instability Estimation Framework for
Microarchitectural Components. International Journal of Parallel Programming
(IJPP). 37(4):417-431.
7. M. Mutyam, F. Wang, K.
Ramakrishnan, N. Vijaykrishnan, M. Kandemir, Y. Xie & M. J. Irwin. July
2009 Process Variation Aware Adaptive Cache Architecture and Management. IEEE
Transactions on Computers (TC). 58(7):865-877.
8.
Hu, J., F. Li, V.
Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. July 2009. Compiler-Directed
Instruction Duplication for Soft Error Detection in Embedded Systems. ACM Transactions on Embedded Computing
Systems 8(4)27:1-27:29.
9.
Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J.
Irwin. 2009. Total Power Optimization for Combinational
Logic Using Genetic Algorithms. To
appear in Journal of VLSI Signal
Processing Systems.
10. Mutyam, M., F. Wang; R.
Krishnan,
11. Eachempati, S., N. Vijaykrishnan,
A. Nieuwoudt, Y. Massoud. April
2009. Predicting the Performance and
Reliability of Future Field Programmable Gate Arrays Routing Architectures with
Carbon Nanotube Bundle Interconnect. IET Circuits, Devices, & Systems
3(2):64-75. (First author supervised by
candidate)
12. Ragheb, T., A. Ricketts, M. Modal, S. Kirolos,
G. Link, N. Vijaykrishnan, Y. Massoud. February 2009. Design of Thermally Robust Clock Trees
using Dynamically Adaptive Clock Buffers.
IEEE Transactions on Circuits and
Systems (TCAS) 56(2):374-383. (Second and fifth authors supervised by
candidate)
13. Srinivasan, S., F. Angiolini, M. Ruggiero,
N. Vijaykrishnan, L. Benini.
September 2008. Exploring Architectural
Solutions for Energy Optimizations in Bus Based SoC. IET Computers & Digital Techniques
2(5):347-354.
14. Celik, C., K. Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M.
J. Irwin, Y. Xie. August 2008. Thermal Neutron Induced Soft Error Rate Measurement
in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear
Chemistry 278(2):509-512. (Third
author supervised and fourth author co-supervised by candidate)
15. Gayasen, A., N.
Vijaykrishnan, M. Kandemir, A. Rahman. July 2008. Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.
IEEE Transactions on VLSI 16(7):882-893. (First author co-supervised by candidate)
16. Yang, S., W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, Y. Xie. July 2008. Case Study of Reliability-Aware
and Low-Power Design. IEEE Transactions on Very Large Scale
Integration (VLSI) 16(7):861-873.
17.
Srinivasan, S.,
R. Krishnan, P. Mangalagiri, Y. Xie, N. Vijaykrishnan, M. J. Irwin, K.
Sarpatwari. April-June 2008. Toward Increasing FPGA Lifetime. IEEE Transactions on Dependable and Secure
Computing 5(2):115-127. (Third three
authors supervised by candidate)
18.
Tsai, Y., F.
Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin.
April 2008. Design Space
Exploration for Three-Dimensional Cache.
IEEE Transactions on VLSI 16(4):444-455. (First author supervised by candidate)
19. Brooks, R., P. Govindaraju, M. Pirretti, N.
Vijaykrishnan, M. Kandemir. November
2007. On the Detection of Clones in
Sensor Networks Using Random Key Predistribution. IEEE
Transactions on Systems, Man, and Cybernetics 37(6):1246-1258. (Third author supervised by candidate)
20. Xie, Y., L. Li, M.
Kandemir, N. Vijaykrishnan, M. J. Irwin. October 2007. Reliability-Aware Co-synthesis for Embedded
Systems. Journal of VLSI Signal Processing 49(1):87-99. (Second author supervised by candidate)
21. Wang, F., M. Debole, X. Wu, Y. Xie, N. Vijaykrishnan,
M. J. Irwin. September 2007. On-chip Bus Thermal Analysis and Optimization. IET
Computer & Digital Techniques 1(5):590-599. (Second author supervised by candidate)
22. Kim, S., N. Vijaykrishnan, M. J. Irwin. August 2007.
Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set
Resolution. Microprocessors and Microsystems 31(5):293-301. (First author
supervised by candidate)
23. Hu, J., N. Vijaykrishnan, M. J. Irwin, M.
Kandemir. July 2007. Optimizing Power
Efficiency in Trace Cache Fetch Unit. IET Computers and Digital Techniques
1(4):334-348. (First author supervised by candidate)
24. Gayasen, S. Srinivasan, N. Vijaykrishnan,
M. Kandemir. 2007. Design of Power-Aware
FPGA Fabrics. International Journal of
Embedded Systems 3(1/2):52-64. (First author co-supervised and second author
supervised by candidate)
25. Pirretti, M., S. Zhu, N. Vijaykrishnan, P. McDaniel,
M. Kandemir, R. Brooks. September 2006. The Sleep Deprivation Attack in Sensor
Networks: Analysis and Methods of Defense. International
Journal of Distributed Sensor Networks 2(3):267-287. (First author supervised by
candidate)
26. Li. T., J. Rubio, L. K.
John, A. Sivasubramaniam,
27. Lee, J., N. Vijaykrishnan, M. J. Irwin. July
2006. Block-Based Frequency Scalable
Technique for Efficient Hierarchical Coding. IEEE Transactions on Signal Processing 54(7):2559-2566. (First
author co-supervised by candidate)
28. Lee, J., N. Vijaykrishnan, M. J. Irwin.
May
2006. Efficient VLSI Implementation of
Inverse Discrete Cosine Transform. IEEE Transactions on Circuits and Systems
for Video Technology 16(5):655-662.
(First author co-supervised by candidate)
29. Lee, J., N. Vijaykrishnan, M. J. Irwin, W. Wolf. February 2006. An Efficient Architecture for Motion
Estimation and Compensation in the Transform Domain. IEEE
Transactions on Circuits and Systems for Video Technology 16(2):191-201. (First author co-supervised by candidate)
30. Zhang, W., Y-F Tsai, D.
31. Vijaykrishnan, N., Xie, Y. January 2006. Reliability concerns in embedded system designs. IEEE Computer. 39(1):118-120. (Invited) (Principal author)
32. Swankowski, E., N. Vijaykrishnan, R. Brooks, M.
Kandemir, M. J. Irwin. 2005. Symmetric Encryption in Reconfigurable and Custom
Hardware. International Journal of
Embedded Systems 1(3/4):205-217. (First author supervised by candidate)
33. Lattanzi, E, A. Gayasen, M. Kandemir, N.
Vijaykrishnan, L. Benini, A. Bogliolo. 2005 Improving
Java performance using dynamic method migration on FPGAs. International Journal of Embedded Systems 1(3/4):228-236.
(First author supervised and second author co-supervised by candidate)
34. Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J.
Irwin. November 2005. Analyzing Data Reuse for Cache
Reconfiguration. ACM Transactions on
Embedded Computing Systems 4(4):851-876. (First
author supervised by candidate)
35. Kadayif,
36. Degalahal, V., L. Li, N. Vijaykrishnan, M. Kandemir,
M. J. Irwin. October 2005. Soft Error Issues in Low Power Caches. IEEE
Transactions on VLSI 13(10):1157-1166. (First author supervised and second author
co-supervised by candidate)
37. Murali, S., T. Theocharides, N. Vijaykrishnan, M. J.
Irwin, L. Benini, G. DeMicheli.
September-October 2005. Analysis
of Error Recovery Schemes for Networks-On-Chips. IEEE
Design and Test of Computers, Special Issue on Networks on Chips
22(5):434-442. (Second author
co-supervised by candidate)
38. Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin.
July 2005. Exploiting Temporal Loads for
Low Latency and High Bandwidth Memory. IEE
Proceeding: Computers and Digital
Techniques 152(4):457-455. (First
author supervised by candidate)
39. Kim, E-J. G. Link, K. H. Yum, N.
Vijaykrishnan, M. Kandemir, M. J. Irwin, C. R. Das. June
2005. A Holistic Approach to Designing
Energy-Efficient Cluster Interconnects. IEEE
Transactions on Computers 54(6):660-671. (Second author supervised by
candidate)
40. Yang, S., W. Wolf, N. Vijaykrishnan.
June 2005. Power and Performance
Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Transactions on Computers 54(6):714-726. (25% contribution)
41. Zhang, W., Y-F. Tsai, M.
Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De.
March 2005. Leakage-Aware
Compilation for VLIW Architectures. IEE
Proceedings: Computers and Digital Techniques
152(2):251-260. (Second author co-supervised by
candidate) (Invited) (Equal contributions)
42. Kadayif,
43. Kim, S., N. Vijaykrishnan,
M. Kandemir, M. J. Irwin. March 2005.
Optimizing Leakage Energy Consumption in Cache Bitlines. Journal of Design Automation for Embedded
Systems (DAEM) 9(1):5-18. (First author supervised by candidate)
44. Tsai, Y-F., D. Duarte, N. Vijaykrishnan, M. J. Irwin. November 2004.
Characterization and Modeling of Run-Time Techniques for Leakage Power
Reduction. IEEE Transactions on Very
Large Scale Integration Systems
12(11):1221-1233. (First author
co-supervised by candidate)
45. Chen, G., B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R.
Chandramouli. September 2004. Studying Energy Tradeoffs in Off-loading
Computation/Compilation in Java-enabled Mobile Devices. IEEE Transactions on Parallel and
Distributed Systems (TPDS) 15(9):795-809. (Second author co-supervised by
candidate)
46. Parikh, A., S. Kim, M. Kandemir, N.
Vijaykrishnan, M. J. Irwin. May
2004. Instruction Scheduling for Low
Power. Journal of VLSI Signal
Processing Systems 37(1):129-149.
(Second
author supervised by candidate) (Equal contributions by authors)
47. Zhang, W.,
J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2004.
Reducing Instruction Cache Energy Consumption Using a Compiler-based
Strategy. ACM Transactions on
Architecture Code Optimization (TACO) 1(1):3-33. (Second and third authors supervised by
candidate)
48. Juran, J., A. R. Hurson, N. Vijaykrishnan, S. Kim. March 2004. Data Organization and Retrieval on Parallel
Air Channels. ACM/Kluwer Wireless
Networks (WINET) Journal 10(2):183-195.
(Contributing author)
49. Kandemir, M., J. Ramanujam,
M. J. Irwin, N. Vijaykrishnan,
50. Kim, S.,
S. Tomar, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. January 2004.
Energy-Efficient Java Execution Using Local Memory and Object
Co-location. IEE Proceedings: Computers
and Digital Techniques 151(1):33-42.
(First two authors supervised by candidate)
51. Kim, N., T. Austin, D.
Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N.
Vijaykrishnan. December 2003. Leakage Current:
52. Saputra, H., N. Vijaykrishnan,
M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang. September 2003. Masking the Energy Behavior of Encryption
Algorithms. IEE Proceedings:
Computers and Digital Techniques 150(5):274-284. (First author co-supervised by
candidate 30% contribution) (Invited among best papers at DATE 2003).
53.
Kim, S., N. Vijaykrishnan, M. Kandemir, A.
Sivasubramaniam, M. J. Irwin. May
2003. Partitioned Instruction Cache
Architecture for Energy Efficiency. ACM
Transactions on Embedded Computing Systems:
Special Issue on Compilers, Architecture, and Synthesis for Embedded
Systems 2(2):163-185. (First author supervised by candidate) (Selected
among best papers from CASES 2001)
54. Li, L,
55. Vijaykrishnan, N., M.
Kandemir, M. J. Irwin, H. Kim, W. Ye.
January 2003. Evaluating
Integrated Hardware-Software Optimizations Using a Unified Energy Estimation
Framework. IEEE Transactions on
Computers 52(1):59-76. (Equal
contributions by authors) (Fourth author supervised by candidate)
56.
Duarte, D., N.
Vijaykrishnan, M. J. Irwin. December
2002. A Clock Power Model to
Evaluate Impact of Architectural and Technology Optimizations. IEEE
Transactions on VLSI 10(6):844-855. (30% contribution) (IEEE CAS
Transactions on VLSI Best Paper Award)
57.
An, N., S. Gurumurthi, A.
Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. December 2002. Energy-Performance Trade-Offs for Spatial
Access Methods on Memory-Resident Data. International
Journal on Very Large Databases 11(3):179-197. (Contributing author) (Invited
among best papers presented at VLDB; 5 out of the 59 papers presented at VLDB
were selected)
58. Chen, G., M.
Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko. November 2002. Tuning Garbage Collection for Reducing Memory
System Energy in an Embedded Java Environment.
ACM Transactions on Embedded Computer Systems 1(1):27-55. (Equal
contributions by authors)
59. Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin and
W. Wolf. October 2002. Using
Memory Compression for Energy Reduction in an Embedded Java System. Journal
of Circuits, Systems and Computers 11(5):537-556. (Equal contributions by
authors)
60. Kandemir, M., N. Vijaykrishnan, M. J. Irwin, W. Ye. December 2001.
Influence of Compiler Optimizations on System Power. IEEE Transactions on VLSI Systems 9(6):801-804. (Equal contributions by authors)
61. De La Luz, V., M. Kandemir, N.
Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin.
November 2001. Hardware and
Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, Special
Issue on Advances in High Performance Memory Systems 50(11):1154-1173. (Equal contributions by authors)
62. Radhakrishnan, R., N.
Vijaykrishnan, L. K. John, A. Sivasubramaniam, J. Rubio, J. Sabarinathan.
February 2001. Java Runtime
Systems: Characterization and
Architectural Implications. IEEE Transactions on Computers.
50(2):131-146. (40% contribution)
63. Esakkimuthu, G., H. S.
Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. February 2001. Investigating Memory System Energy Behavior
Using Software and Hardware Optimizations.
Special Issue in Low Power System Design of VLSI DESIGN. 12(2):151-165. (First/second author supervised by candidate)
64. Bishop, B., V.
Lyuboslavsky, N. Vijaykrishnan, M. J. Irwin.
February 2001. Design Considerations for Databus Charge Recovery. IEEE Transactions on Very Large Scale
Integration Systems 9(1):104-106.(Second author supervised).
65. Vijaykrishnan, N., N. Ranganathan. November 2000. Supporting Object Accesses in a Java
Processor. Proceedings of IEE -
Computers and Digital Techniques Journal 147(6):435-443. (Principal author)
66. Chandramouli, R., N. Vijaykrishnan, N.
Ranganathan. December 1998. Sequential Tests for Integrated Circuit Failure
Analysis. IEEE Transactions on Reliability 47(4):463-471. (Equal
contributions by authors)
67. Ranganathan, N., N. Vijaykrishnan, N. Bhavanishankar. August 1998. A
Linear Array Processor with Dynamic frequency Clocking for Image Processing
Applications. IEEE Transactions on
Circuits and Systems for Video Technology. 8(4):435-445. (Principal author)
b. Articles published in refereed proceedings.
1. Yanamandra, A., N. Vijaykrishnan and M. J. Irwin. Jan
2010. Optimizing Power and Performance for Reliable On-Chip Networks. 15th
2. Singh, J., K. Ramakrishnan, S. Mookerjea, S. Datta, N.
Vijaykrishnan and D. Pradhan, Jan 2010. A Novel Si-Tunnel FET SRAM Design for
Ultra Low-Power 0.3V VDD Application. 15th
3. Saripalli, V.,S. Datta
and N. Vijaykrishnan. Jan 2010. Analyzing
Energy-Delay Behavior in Room Temperature Single Electron Transistors. International Conference on VLSI
4. Mishra, A. K.,
R. Das, S. Eachampati, N. Vijaykrishnan, C. R. Das. Dec 2009. A Case for
Dynamic Frequency Tuning in On-Chip Networks. The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO,
2009).
5. V. Saripalli, N. Vijaykrishnan and S. Datta. October
2009. Ultra Low Energy Binary Decision Diagram Circuits using Few Electron
Transistors. Workshop on Nano-Bio Sensing Paradigms and Applications (in
conjunction with Nanonet 2009)..
6. Al Maashri, A., G. Sun, X. Dong, V. Narayanan, Y. Xie. October 2009. 3D GPU Architecture using Cache Stacking: Performance,
Cost, Power, and Thermal Analysis. International Conference on Computer
Design (ICCD).
8. Xie, Y., S.
Eachempati, A. Yanamandra, N. Vijaykrishnan, M. J. Irwin. July 2009. Power and
area reduction using carbon nanotube bundle interconnect in global clock tree
distribution network. IEEE/ACM International Symposium on Nanoscale
Architectures. 51-56
9. Bae, S., R. Krishnan, N. Vijaykrishnan. A Novel Low
Area Overhead Body Bias FPGA Architecture for Low Power Applications. IEEE Computer Society Annual Symposium on
VLSI, pp.193-198,
10. Mangalagiri, P., N. Vijaykrishnan, May 2009. Lifetime
Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. IEEE Computer Society Annual Symposium on VLSI,
pp.61-66.
11. Bae, S., P. Mangalagiri, N. Vijaykrishnan. April 2009.
Exploiting Clock Skew Scheduling
for FPGA. Proceedings of the Design Automation & Test in
12. Das, R., S. Eachempati, A. K. Mishra, N.
Vijaykrishnan, C. R. Das. February
2009. Design and Evaluation of a
Hierarchical On-Chip Interconnect for Next-Generation CMPs. Proceedings
of the Fifteenth International Symposium on High-Performance Computer
Architecture (HPCA-15). pp.
175-186.
13. Yanamandra, A., M. J. Irwin, N. Vijaykrishnan, M.
Kandemir, S. H. K. Narayanan. January 2009.
In-Network Caching for Chip
Multiprocessors. Proceedings of
the Fourth International Conference on High Performance Embedded Architectures
and Compilers (HiPEAC 2009).
Springer-Verlag LNCS 5409:373-388.
14. Sridharan, S., M. DeBole, G. Sun, Y. Xie, N. Vijaykrishnan.
January 2009. A Criticality-Driven Microarchitectural Three Dimensional (3D)
Floorplanner. Proceedings of the Fourteenth
15. DeBole, M., R. Krishnan, V. Balakrishnan, W. Wang, L.
Hong, Y. Wang, Y. Xie, Y. Cao,
16. Henkel, J., N. Vijaykrishnan, S. Parameswaran, R.
Ragel. January 2009. Security and Dependability of Embedded
Systems: A Computer Architects
Perspective. Proceedings of the Twenty-Second International Conference on VLSI
Design (VLSI Design 2009). pp. 30-32. New Delhi, India.
17. Saripalli, V, S.
Mookerjea, S. Datta, N. Vijaykrishnan. November
2008. Ultra low power signal processing architectures. IEEE Biomedical Circuits and Systems Conference. pp.333-336,
18. Mangalagiri, P., S. Bae, R. Krishnan, N.
Vijaykrishnan, Y. Xie, T. Tuan. November 2008.
Thermal-Aware Reliability Analysis for Platform FPGAs. Proceedings of the International Conference
on Computer Aided Design (ICCAD 2008).
pp. 722-727.
19. Ramakrishnan, K., N. Vijaykrishnan, Y. Xie. October 2008.
Comparative Analysis of NBTI
Effects on Low Power and High Performance Flip-Flops. Proceedings of the
XXVI International Conference
on Computer Design (ICCD 2008). pp.
200-208.
20. Deng, L., C-L. Yu, C. Chakrabarti, J. Kim, N.
Vijaykrishnan. October 2008. Efficient Image Reconstruction Using Partial
2D Fourier Transform. Proceedings of the
2008 IEEE Workshop on Signal Processing Systems (SIPS 2008). pp.
49-54.
21. Soundarajan, N., N. Vijaykrishnan, A. Sivasubramaniam. August 2008. Impact of DVFS on the Architectural Vulnerability
of GALS Architctures. Proceedings of the International
Symposium on Low Power
Electronics and Design (ISLPED 2008). pp. 351-356.
22. Soundararajan, N., A. Yanamandra, C. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. June 2008.
Analysis and Solutions to Issue Queue Process Variation. Proceedings
of the Thirty-Eighth Annual IEEE/IFIP International Conference on Dependable
Systems and Networks (DSN 2008). pp.
11-21.
23. Park, D., S. Eachempati, R. Das, A. K Mishra, N. Vijaykrishnan, Y. Xie, C. R Das. June 2008.
MIRA: A Multi-Layered On-Chip Interconnect Router Architecture. Proceedings of the International Symposium
on Computer Architecture (ISCA 2008).
pp. 251-261.
24. Eachempati,
S.,
V. Saripalli, N. Vijaykrishnan, S.
Datta. June
2008. Reconfigurable BDD Based Quantum
Circuits. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch 2008). pp.
61-67.
25. Mangalagiri, P., K. Sarpatwari, A. Yanamandra, N. Vijaykrishnan, Y. Xie, M. J. Irwin, O. A. Karim. May 2008.
A low-power Phase Change Memory Based Hybrid Cache Architecture. Proceedings of the ACM
26. Irick, K.,
27. Krishnan, R., R. Ramanarayanan,
N. Vijaykrishnan, Y. Xie,
M. J. Irwin, K. Unlu.
March 2008. Hierarchical Soft Error Estimation Tool (HSEET). Proceedings
of the Ninth International Symposium on Quality Electronic Design (ISQED 2008). pp. 680-683.
28. Das, R., A. K. Mishra, C. Nicopoulos, D. Park, N.
Vijaykrishnan, R. Iyer, C. R. Das.
February 2008. Performance and
Power Optimization through Data Compression in Network-on-Chip Architectures. Proceedings
of the Fourteenth International Symposium on High Performance Computer
Architecture (HPCA 2008). pp.
215-225.
29. Atienza, D., G. De
Micheli, L. Benini, J. L. Ayala, P. G. Del Valle, M. DeBole, N. Vijaykrishnan. January 2008.
Reliability-Aware Design for Nanometer-Scale Devices. Proceedings
of the Thirteenth IEEE/ACM
30. F. Wang, C. Nicopoulos, X. Wu, Y. Xie, N.
Vijaykrishnan. Nov. 2007. Variation-aware Task Allocation and Scheduling for
MPSoC. International Conference on
Computer Aided Design (ICCAD), pp. 598-603.
31. S. Srinivasan,
P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. Oct. 2007. FPGA Routing Architecture Analysis Under
Variations. International Conference on
Computer Design (ICCD), pp.152-157.
32. C. Nicopoulus, A. Yanamandra, S. Srinivasan, N.
Vijaykrishnan and M. J. Irwin. 2007. Variation-Aware Issue Queue Design. Forty-First Asilomar Conference on Signals,
Systems and Computers. pp. 1402-1406.
33. Irick, K., M. DeBole, N. Vijaykrishnan, R. Sharma, H.
Moon, S. Mummareddy. August 2007. A Unified
Streaming Architecture for Real Time Face Detection and Gender Classification. Proceedings of the Seventeenth International
Conference on Field Programmable Logic and Applications (FPL 2007). pp.
267-272.
34. Kim, J., P. Mangalagiri, K.
Irick, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N.
Pitsianis, X. Sun. August 2007. TANOR: A Tool for Accelerating N-Body
Simulations on Reconfigurable Platform. Proceedings
of the Seventeenth International Conference on Field Programmable Logic and
Applications (FPL 2007). pp.
68-73.
35. Park, D., R. Das, C. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, C. R.
Das. August 2007. Design of a Dynamic
Priority-Based Fast Path Architecture for On-Chip Interconnects. Proceedings
of the Fifteenth Annual IEEE Symposium on High-Performance Interconnects (HOTI
2007). pp. 15-20.
36. Kim, J., C. Nicopoulos, D. Park, R. Das, Y. Xie, N.
Vijaykrishnan, C. R. Das. June
2007. A Novel Dimensionally-Decomposed
Router for On-Chip Communication in 3D Architectures. Proceedings
of the Thirty-Fourth Annual International Symposium on Computer Architecture
(ISCA 2007). pp. 138-149.
37. Ricketts, A., M. Mutyam, N. Vijaykrishnan, M. J.
Irwin. May 2007. Investigating Simple Low Latency Reliable
Multiported Register Files. Proceedings of the IEEE Computer Society
Annual Symposium on VLSI (ISVLSI 2007).
pp. 375-382. Porte
38. Mondal, M., A. Ricketts, S. Kirolos, T. Ragheb, G. Link,
N. Vijaykrishnan, Y. Massoud. April
2007. Thermally Robust Clocking Schemes
for 3D Integrated Circuits. Proceedings of the Design, Automation and
Test in
39. Mutyam, M., N. Vijaykrishnan. April 2007.
Working with Process Variation Aware Caches. Proceedings
of the Design, Automation and Test in
40. Eachempati, S., A. Nieuwoudt, A. Gayasen, Y. Massoud,
N. Vijaykrishnan. April 2007. Assessing Carbon Nanotube Bundle Interconnect
for Future FPGA Architectures. Proceedings
of the Design, Automation and Test in
41. Krishnan, R., R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan,
Y. Xie, M. J. Irwin. March 2007. Variation
Impact on SER of Combinational Circuits.
Proceedings of the International
Society for Quality Electronic Design (ISQED 2007). pp. 911-916.
42. Mupid, A., M. Mutyam, N. Vijaykrishnan, Y. Xie, M. J.
Irwin. March 2007. Variation Analysis of
43. Mondal, M., A. Ricketts, S. Kirolos, T. Ragheb, G. Link,
N. Vijaykrishnan, Y. Massoud. March
2007. Mitigating Thermal Effects on
Clock Skew with Dynamically Adaptive Drivers.
Proceedings of the International
Society for Quality Electronic Design (ISQED 2007). pp. 67-72.
44. Ramakrishnan, R S. Srinivasan, N. Vijaykrishnan, Y.
Xie. January 2007. Impact of NBTI on FPGAs. Proceedings
of the International Conference on VLSI Design. pp. 717-722.
45. Vaidyanathan, B., W. Hung, F. Wang, Y. Xie, N.
Vijaykrishnan, M. J. Irwin. January 2007. Architecting Microprocessor
Components in 3D Design Space. Proceedings
of the Twentieth International Conference on VLSI Design. pp. 103-108.
46. Nicopoulos, C. A., D. Park, J. Kim, N. Vijaykrishnan, C. R. Das. December
2006. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip
Routers. Proceedings of the International Symposium on Microarchitecture (MICRO 06).
pp. 333-346.
47. Vaidyanathan, B., Y. Xie, N. Vijaykrishnan, R. Luo. December
2006. Leakage Optimized DECAP Design for FPGAs. Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems
(APCCAS 2006). pp. 960-963.
48. Sundararajan, P. A. Gayasen, N. Vijaykrishnan, T. Tuan. November 2006. Thermal Characterization and Optimization in
Platform FPGAs. Proceedings International
Conference on Computer Aided Design (ICCAD-2006). pp. 443-447.
49. Sundararajan, P, S.
Krishnamurthy,
50. Chen, G, L. Xue, J. Kim, K.
Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N.
Vijaykrishnan. September 2006. Using Geometric Tiling for Reducing Power
Consumption in Structured Matrix Operations. Proceedings of the IEEE International System on Chip Conference (SOCC
2006). pp. 113-114.
51.
Srinivasan, S., R. Ramadoss, N. Vijaykrishnan. September 2006. Process
Variation Aware Parallelization Strategies for MPSoCs. Proceedings of the IEEE International System on Chip Conference (SOCC
2006). pp. 179-184.
52. Park, D., C. Nicopoulos, J. Kim,
N. Vijaykrishnan, C. R. Das. September
2006. A Distributed
53. Srinivasan, S., M. Prasanth,
S. Karthink, Y. Xie, N. Vijaykrishnan.
July 2006. FLAW: FPGA Lifetime Awareness.
Proceedings of the Forty-Third Design
Automation Conference (DAC 2006). pp.
630-635.
54. Park, D., C. A. Nicopoulos, J. Kim, N. Vijaykrishnan,
C. R. Das. June 2006. Exploring Fault-Tolerant Network-on-Chip
Architectures. Proceedings of the International Conference on Dependable Systems and
Networks DCCS Track (DSN-2006). pp. 93-102.
55. Li, F., C. Nicopoulos, T. Richardson, Y. Xie, N.
Vijaykrishnan, M. Kandemir. June 2006. Design and Management of 3D Chip Multiprocessors
using Network-in-memory. Proceedings of the Thirty-Third Annual International Symposium on Computer
Architecture (ISCA 2006). pp. 130-141.
56. Kim, J., C. A. Nicopoulos, D. Park, N. Vijaykrishnan,
C. R. Das. June 2006. A Gracefully Degrading and Energy-Efficient
Modular Router Architecture for On-Chip Networks. Proceedings
of the Thirty-Third Annual International Symposium on Computer Architecture
(ISCA 2006). pp. 4-15.
57. Mutyam, M., F. Li, N.
Vijaykrishnan, M. Kandemir, M.J. Irwin.
June 2006. Compiler Directed
Thermal Management for VLIW Functional Units.
Proceedings of the ACM
SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded
Systems (LCTES 2006). pp. 163-172.
58.
Gayasen, A., N. Vijaykrishnan,
M. Kandemir, A. Rahman. April 2006. Switch Box Architectures for
Three-Dimensional FPGAs. Proceedinsg of the IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM). 2 pages.
59. Ramanarayanan, R., Krishnan,
N. Vijaykrishnan, Y. Xie, M. J. Irwin.
April 2006. Temperature and
Voltage Scaling Effects on Electrical Masking.
Proceedings of the Second Workshop
on System Effects of Logic Soft Errors (SELSE 2006). 4 pages.
60. Vaidyanathan, B., Y. Xie, N.
Vijaykrishnan, H. Zheng. April 2006. Soft Error Analysis and Optimizations of
C-elements in Asynchronous Circuits. Proceedings of the Second Workshop on System Effects
of Logic Soft Errors (SELSE 2006). 4
pages.
61. Lin,
62. Link, G., N. Vijaykrishnan. March 2006.
Thermal Trends in Emerging Technologies.
Proceedings of the Seventh
International Symposium on Quality Electronic Design (ISQED 2006). pp. 625-632.
63. Hung, W.-L., G. Link, Y. Xie, N. Vijaykrishnan, M. J.
Irwin. March 2006. Interconnect and Thermal-aware Floorplanning
for 3D Microprocessors. Proceedings of the Seventh International
Symposium on Quality Electronic Design (ISQED 2006). pp. 98-104.
64. Wang, F., Y. Xie, N.
Vijaykrishnan, M. J. Irwin. March 2006. On-chip
Bus Thermal Analysis and Optimization. Proceedings of the Design, Automation and
Test in
65. Ricketts, A. J., K. Irick, N. Vijaykrishnan, M. J.
Irwin. March 2006. Priority Scheduling in Digital
Microfluidics-Based Biochips. Proceedings of the Design, Automation and
Test in
66. Kim, J., C. A. Nicopoulos, D. Park, N. Vijaykrishnan,
C. R. Das. March 2006. Performance Enhancement through Early Release
and Buffer Optimization in Network-on-Chip Router Architectures. Special
Workshop on Future Interconnects and Networks on Chip, in conjunction with
the Design, Automation and Test in
67. Theocharides, T., N. Vijaykrishnan, M. J. Irwin. March 2006.
A Parallel Architecture for Hardware Face Detection. Proceedings
of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006).
pp. 452-454.
68. Srinivasan, S., N. Vijaykrishnan. March 2006.
Variation Aware Placement Scheme for FPGAs. Proceedings
of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). pp.
422-424.
69. Mutyam, M., M. Eze, N. Vijaykrishnan, Y. Xie. March 2006.
Delay and Energy Efficient Data Transmission for On-Chip Buses. Proceedings
of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006).
pp. 355-360.
70. Yang, S., W. Wolf, N. Vijaykrishnan, Y. Xie. March 2006.
71. Chen, G., G. Chen, M.
Kandemir, N. Vijaykrishanan, M. J. Irwin. January
2006. Object Duplication for Improving
Reliability. Proceedings of the Eleventh
72. Richardson, T., C. Nicopolus, N. Vijaykrishnan, D.
Park, Y. Xie C. R. Das. January 2006. A Hybrid SoC Interconnect with Dynamic
TDMA-Based Transaction-Less Buses and On-Chip Networks. Proceedings
of IEEE International Conference on VLSI Design. pp. 657-664.
73. Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Y.
Xie, M. J. Irwin. January 2006. SEAT-LA:
A Soft Error Analysis tool for Combinational Logic. Proceedings of Nineteenth International Conference on VLSI Design. pp. 499-502.
74. Kim, J., D. Park, C.
Nicopoulus, N. Vijaykrishnan, C. R. Das. October 2005. Design and Analysis of
an NoC Architecture from Performance, Reliability and Energy Perspective. Proceedings
of the First Symposium on Architectures for Networking and Communication
Systems (ANCS 2005). pp. 173-182.
75. Pirretti, M. , N. Vijaykrishnan, M. Kandemir, R.
Brooks. October 2005. Realistic Models for Sensor Networks Using
Key Predistribution Schemes. Proceedings of the Innovations and
Commercial Applications of Distributed Sensor Networks Symposium (
76. Pirretti, M., S. Zhu, N. Vijaykrishnan, P. McDaniel,
M. Kandemir, R. Brooks. October
2005. The Sleep Deprivation Attack in
Sensor Networks: Analysis and Methods of Defense. Proceedings of the Innovations and Commercial Applications of
Distributed Sensor Networks Symposium (
77. Hung, W., G. Link, Y. Xie,
N. Vijaykrishnan, N. Dhanwada J. Conner. October 2005.
78. Tsai, Y., Y. Xie, N.
Vijaykrishnan, M. J. Irwin. October 2005. Three-dimensional cache design using
3DCacti. Proceedings of the IEEE International Conference on Computer Design
(ICCD 2005). pp. 519-524.
79. Dhanwada, N.,
80. Srinivasan, S., F.
Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2005. Simultaneous Memory and Bus Partitioning for SoC
Architectures. Proceedings of the IEEE International SoC Conference (SOCC 2005). pp. 125-128.
81. Swankowski, E., N.
Vijaykrishnan. September 2005. Dynamic High-Performance Multi-Mode
Architectures for AES Encryption. Proceedings of the Annual Military and
Aerospace Applications of Programmable Devices and Technologies Conference
(MAPLD'05). (CD ROM Proceedings).
82. Veezhinathan, K., Sk. Noor Mahammad, V. Muralidaran,
N. Vijaykrishnan and V. Chandrasekar. September
2005. Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGA. Proceedings
of the Annual Military and
Aerospace Applications of Programmable Devices and Technologies Conference
(MAPLD'05). (CD ROM Proceedings).
83. Gayasen, A., N. Vijaykrishnan, M. J. Irwin. June 2005.
Exploring Technology Alternatives for Nano-Scale FPGA
Interconnects. Proceedings of the Forty-Second Design Automation Conference (DAC'05).
pp. 921-926.
84. Kim, J-H., D. Park, T. Theocharides, N. Vijaykrishnan,
C. R. Das. June 2005. A Low Latency Router Supporting Adaptivity
for On-Chip Interconnects. Proceedings of the Forty-Second Design
Automation Conference (DAC'05). pp. 559-564.
85. Saputra, H., O. Ozturk, N. Vijaykrishnan, M. Kandemir,
R. Brooks. May 2005. A Data-driven Approach for Embedded
Security. Proceedings of the IEEE Computer Society Annual Symposium on VLSI
(ISVLSI '05). pp. 104-109.
86. Lee, J., N. Vijaykrishnan, M. J. Irwin. May 2005.
High Performance Array Processor for Video Decoding. Proceedings
of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '05). pp. 28-33.
87. Reddy, S. S., E., V. Chandrasekhar, M. Sashikanth, V.
Kamakoti Veezhinathan, N. Vijaykrishnan.
April 2005. Online Detection and
Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs. Proceedings
of the Twelfth Reconfigurable Architectures Workshop (RAW 2005). p. 172a.
88. Hung, W-L., Y. Xie, N. Vijaykrishnan, C. Addo-Quaye,
T. Theocharides, M. J. Irwin. March
2005. Thermal-Aware Floorplanning Using
Genetic Algorithms. Proceedings of
the Sixth International Symposium on Quality Electronic Design (ISQED 2005).
pp. 634-639.
89. Hu, J., F. Li, V. Degalahal, M. Kandemir, N.
Vijaykrishnan, M. J. Irwin. March
2005. Compiler-directed Instruction
Duplication for Soft Error Detection. Proceedings of the Design, Automation, and
Test in
90. Hung, W-L., Y. Xie, N.
Vijaykrishnan, M. Kandemir, M. J. Irwin.
March 2005. Thermal-Aware Allocation and Scheduling for
Systems-on-a-Chip Design. Proceedings of the Design, Automation, and
Test in
91. Link, G., N. Vijaykrishnan. March 2005. Hotspot
Prevention Through Runtime Reconfiguration in Network-On-Chip Designs. Proceedings
of the Design, Automation, and Test in
92. Tsai, Y-F., N. Vijaykrishnan, Y. Xie, M. J.
Irwin. March 2005. Leakage-Aware Interconnect for On-Chip
Network. Proceedings of the Design, Automation, and Test in
93. Srinivasan, S., N. Vijaykrishnan. March 2005.
Simultaneous Partitioning and Frequency Assignment for On-chip Bus
Architectures. Proceedings of the Design, Automation, and Test in
94. Yang, S., W. Wolf, N. Vijaykrishnan, Y. Xie. March 2005.
Power Attack Resistant Crypto Design:
A Dynamic Voltage and Frequency Switching Approach. Proceedings
of the Design, Automation, and Test in
95. Reddy, S. S., E., V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N.
Vijaykrishnan. January 2005. Cluster-based Detection of SEU-caused Errors
in LUTs of SRAM-based FPGAs. Proceedings of the
96. Srinivasan,
S., A. Gayasen, N. Vijaykrishnan, T. Tuan.
January 2005. Leakage Control in
FPGA Routing Fabric. Proceedings of
the
97. Yang, S., W. Wolf, W. Wang, N. Vijaykrishnan, Y.
Xie. January 2005. Low-Leakage Robust SRAM Cell Design for Sub-100nm
Technologies. Proceedings of the
98. Reddy, S. S., E., S., M. Sashikanth, V. Chandrasekhar,
99. Tsai, Y-F., N. Vijaykrishnan, M. J. Irwin, Y.
Xie. January 2005. Influence of Leakage Reduction Techniques on
Delay/Leakage Uncertainty. Proceedings of the
Eighteenth International Conference on VLSI Design. pp. 374-379.
100.
Irick, K., W. Xu,
N. Vijaykrishnan, M. J. Irwin. January
2005. A Nanosensor Array Based VLSI Gas
Discriminator. Proceedings of the
Eighteenth International Conference on VLSI Design. pp. 241-248.
101.
Yang, S., W.
Wolf, W. Wang, N. Vijaykrishnan, Y. Xie.
January 2005. Accurate Stacking
Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. Proceedings of the Eighteenth International
Conference on VLSI Design. pp. 165-170.
102.
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin. January 2005.
Implementing LDPC Decoding on Network on Chip. Proceedings of the Eighteenth
International Conference on VLSI Design.
pp. 134-137.
103.
Reddy, S. S., E.,
S. Kanth, V. Chandrasekhar, S. Srinivasan, N. Vijaykrishnan, V. Kamakoti.
December 2004. A Novel CLB Architecture
to Detect and Correct SEU in LUTs of SRAM-based FPGAs. Proceedings of the
2004 IEEE International Conference on Field- Programmable Technology (FPT'04). pp. 121-128.
104.
Kim, J. S., C. Nicopoulos, N. Vijaykrishnan, Y. Xie, E. Lattanzi. November 2004. A Probabilistic Model for Soft-Error Rate
Estimation in Combinatorial Logic. Proceedings
of the First International Workshop on Probabilistic Analysis Techniques for
Real Time and Embedded Systems (PARTES 2004).
105.
Unlu, K., V. Degalahal, M. S. Cetiner, N. Vijaykrishnan, M. J.
Irwin. November 2004. Testing Neutron-Included Soft Errors in Semiconductors. Proceedings of the American Nuclear
Society Winter Meeting. pp.
825-826.
106.
Srinivasan, S., A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M.
J. Irwin. November 2004. Improving Soft-error Tolerance of FPGA
Configuration Bits. Proceedings of the International Conference on Computer Aided Design
(ICCAD-2004). pp. 107-110.
107.
Kang, B. T., N. Vijaykrishnan,
M. J. Irwin. November 2004. Analyzing Software Influences on Substrate
Noise: An ADC Perspective. Proceedings
of the International Conference on Computer Aided Design (ICCAD-2004). pp. 916-922.
108.
Chen, G., M. Kandemir, N.
Vijaykrishnan, M. J. Irwin. October 2004. Field-level Analysis for Heap Space
Optimization in Embedded Java. Proceedings of the International Symposium
on Memory Management (ISMM'04). pp.
131-142.
109.
Lee, J., N. Vijaykrishnan, M. J. Irwin, R. Radhakrishnan. October 2004.
Inverse Discrete Cosine Transform Architecture Exploiting Sparseness and
Symmetry Properties. Proceedings of the IEEE Workshop on Signal
Processing Systems (SiPS'04). pp.
361-366.
110.
Hung, W., C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M.
J. Irwin. October 2004. Thermal-Aware IP Virtualization and Placement
for Networks-on-Chip Architecture. Proceedings of the International Conference
on Computer Design (ICCD 2004). pp.
430-437.
111.
Xie, Y., L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. September 2004. Reliability-aware Cosynthesis for Embedded
Systems. Proceedings of the Fifteenth IEEE International Conference on
Application-Specific Systems, Architectures, and Processors (ASAP'04). pp. 41-50.
112.
Tsai, Y-F., A. Hegde, N. Vijaykrishnan, M. J. Irwin. September 2004. ChipPower:
An Architecture-Level Leakage Simulator.
Proceedings of the IEEE
International Systems-on-Chip Conference (SOCC 2004). pp. 395-398.
113.
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin, V.
Srikantam. September 2004. A Generic Reconfigurable Neural Network
Architecture Implemented as a Network on Chip.
Proceedings of the IEEE
International Systems-on-Chip Conference (SOCC 2004). pp. 191-194.
114.
Kang, B. T., N. Vijaykrishnan, M. J. Irwin, T. Theocharides. September 2004. Power-Efficient Implementation of Turbo
Decoder in SDR Systems. Proceedings of the IEEE International
Systems-on-Chip Conference (SOCC 2004).
pp. 119-122.
115.
Chen, G., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J.
Irwin. September 2004. Analyzing Object Error Behavior in Embedded
JVM Environments. Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software
Codesign and Systems Synthesis (CODES+ISSS'04). pp. 230-235.
116.
Gayasen, A., K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T.
Tuan. August-September 2004. A Dual Vdd Low-power FPGA Architecture. Proceedings
of the International Conference on Field-programmable Logic and Its
Applications (FPL'04). pp.
145-157.
117.
Hung, W., Y. Xie, N. Vijaykrishnan, M. Kandemir, M.
J. Irwin. August 2004. Total Power Optimization Through
Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With
Stack Forcing. Proceedings of the
International Symposium on Low Power Electronics and Design (ISLPED 2004). pp. 144-149.
118.
Li, L., V. Degalahal, N. Vijaykrishnan, M. Kandemir,
M. J. Irwin. August 2004. Soft Error and Energy Consumption
Interactions: A Data Cache
Perspective. Proceedings of the
International Symposium on Low Power Electronics and Design (ISLPED 2004). pp. 132-137.
119.
Yang, S., W. Wolf, N. Vijaykrishnan.
June 2004. Search Speed and Power
Driven Integrated Software and Hardware Optimizations for Motion Estimation
Algorithms. Proceedings of the 2004
IEEE International Conference on Multimedia and Expo (ICME 2004). pp. 707-710.
120.
Saputra, H., G. Chen, R.
Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2004.
Code Protection for Resource-constrained Embedded Devices. Proceedings of the ACM SIGPLAN/SIGBED 2004
Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '04). pp. 240-248.
121.
Tsai, Y-F., D. Duarte, N.
Vijaykrishnan, M. J. Irwin. May 2004. Impact of Process Scaling on the Efficacy of
Leakage Reduction Scheme. Proceedings of the International Conference
on IC Design and Technology (ICICDT 2004).
pp. 3-11.
122.
Lee, J., N. Vijaykrishnan, M. J. Irwin.
May 2004. Efficient VLSI
Implementation of Inverse Discrete Cosine Transform. Proceedings of the International
Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004). pp. 177-180.
123.
Xu, W., N. Vijaykrishnan, Y. Xie, M. J. Irwin. April 2004.
Design of a Nanosensor Array Architecture. Proceedings of the 2004
124.
Lattanzi, E., A. Bogliolo, A.
Gayasen, M. Kandemir, N. Vijaykrishnan, L. Benini. April 2004.
Improving Java Performance by Dynamic Method Migration on FPGAs. Proceedings of the Eleventh Reconfigurable
Architectures Workshop (RAW 2004).
p. 134.
125.
Swankoski, E., R. Brooks, N.
Vijaykrishnan, M. Kandemir, M. J. Irwin.
April 2004. A Parallel
Architecture for Secure FPGA Symmetric Encryption. Proceedings of the Eleventh Reconfigurable
Architectures Workshop (RAW 2004).
p. 132.
126.
Degalahal,
R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2004.
The Effect of Threshold Voltages on the Soft Error Rate. Proceedings of the Fifth International
Symposium on Quality Electronic Design (ISQED 2004). pp. 503-508.
127.
Gayasen, A., Y. Tsai, N.
Vijaykrishnan, M. Kandemir, M. J. Irwin.
February 2004. Reducing Leakage
Energy in FPGAs Using Region-constrained Placement. Proceedings of the ACM International
Symposium on Field-Programmable Gate Arrays (FPGA'04). pp. 51-58.
128.
Theocharides, T., G. Link, E. Swankoski, N. Vijaykrishnan, M. J. Irwin,
H.Schmit. February 2004. Evaluating Alternative Implementations for
LDPC Decoder Check Node Function. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI
2004).
pp. 77-82.
129.
Pirreti, M., G. Link, R.
Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2004. Fault-tolerant Algorithms for Network-on-chip
Interconnect. Proceedings of the IEEE
Computer Society Annual Symposium on VLSI (ISVLSI 2004). pp. 46-51.
130.
Kadayif, I.,
131.
Hu, J. S., N. Vijaykrishnan, S.
Kim, M. Kandemir, M. J. Irwin. February
2004. Scheduling Reusable Instructions
for Power Reduction. Proceedings of
the Design Automation and Test in
132.
Li, L., N. Vijaykrishnan, M.
Kandemir, M. J. Irwin. February
2004. A Crosstalk Aware Interconnect
with Variable Cycle Transmission. Proceedings
of the Design Automation and Test in
133.
Hu, J. S., N. Vijaykrishnan, M.
J. Irwin. February 2004. Exploring Wakeup-Free Instruction
Scheduling. Proceedings of the Tenth
International Symposium on High Performance Computer Architecture (HPCA-10). pp. 232-243.
134.
Lee, J., N. Vijaykrishnan, M.
J. Irwin, W. Wolf. January 2004. An Architecture for Motion Estimation in the
Transform Domain. Proceedings of the
Seventeenth International Conference on VLSI Design. pp. 1077-1082.
135.
Derenzo, M., M. J. Irwin, N.
Vijaykrishnan. January 2004. Designing Leakage-Aware Multipliers. Proceedings of the
Seventeenth International Conference on VLSI Design. pp. 654-657.
136.
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin, W. Wolf. January 2004.
Embedded Hardware Face Detection.
Proceedings of the Seventeenth International Conference on VLSI
Design. pp. 133-138.
137.
Yang, S., W. Wolf, N. Vijaykrishnan.
December 2003. Power Modeling of
VLSI Motion Estimation Architecture. Proceedings
of the Fifth Workshop on Media and Streaming Processors (MSP), held in
conjunction with MICRO-6. pp.
39-49.
138.
Vijaykrishnan, N. December
2003. Designing Energy-Efficient and
Reliable Hardware. Proceedings of the
IFIP International Conference on VLSI.
pp. 6-9.
139.
Li, L., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. November 2003. Adaptive Error Protection for Energy
Efficiency. Proceedings of the
International Conference on Computer Aided Design (ICCAD-2003). pp. 2-7.
140.
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, B. Mathiske, M.
Wolczko. October 2003. Heap Compression
for Memory-constrained Java Environments.
Proceedings of the Eighteenth Annual ACM SIGPLAN Conference on
Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'03). pp. 282-301.
141.
De La Luz, V., A. Sivasubramaniam, M. Kandemir, M. J. Irwin, N.
Vijaykrishnan. October 2003. Reducing dTLB Energy Through Dynamic
Resizing. Proceedings of the
Twenty-First International Conference on Computer Design (ICCD). pp. 358-363.
142.
Chen, G., N. Vijaykrishnan, M.
Kandemir, M. J. Irwin, M. Wolczko. October 2003. Tracking Object Life Cycle for Leakage Energy
Optimization. Proceedings of the CODES-ISSS
Merged Conference (CODES/ISSS'03). pp.
213-218.
143.
Hegde, A., N. Vijaykrishnan, M.
Kandemir, M. J. Irwin. October 2003. VL-CDRAM: Variable
Line Sized Cached DRAMs. Proceedings
of the CODES-ISSS Merged Conference (CODES/ISSS'03). pp. 132-137.
144.
145.
Kang, B., N. Vijaykrishnan, M. J. Irwin, D.
146.
Ramanarayanan, R., V. Degalahal, N. Vijaykrishnan, M. J. Irwin, D.
147.
Chen, G., G. Chen, M. Kandemir,
N. Vijaykrishnan, M. J. Irwin. September 2003. Energy-aware
Code Cache Management for Memory-constrained Java Devices. Proceedings of the IEEE International SOC
Conference (ASIC/SOC'03). pp.
179-182.
148.
Li, L., N. Vijaykrishnan, M. Kandemir, M. J. Irwin,
149.
Lee, J., N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. August 2003.
An Efficient Implementation of Hierarchical Image Coding. Proceedings of the IEEE Workshop on Signal
Processing Systems (SIPS'03). pp.
363-368.
150.
Saputra, H., N. Vijaykrishnan, M. Kandemir, R. Brooks, M. J.
Irwin. August 2003. Exploiting Value Locality for Secure Energy
Aware Communication. Proceedings of
the IEEE Workshop on Signal Processing Systems (SIPS'03). pp. 116-121.
151.
Kim, E. J., K. H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M. J.
Irwin, C. R. Das. August 2003. Energy Optimization Techniques in Cluster
Interconnects. Proceedings of the International Symposium on Low Power
Electronics and Design (ISLPED'03).
pp. 459-464.
152.
Hu, J. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. August 2003.
Exploiting Program Hotspots and Code Sequentiality for Instruction Cache
Leakage Management. Proceedings of
the International Symposium on Low Power Electronics and Design (ISLPED'03). pp. 402-407.
153.
Kim, S., N. Vijaykrishnan, M. J. Irwin, L. K. John. August 2003.
On Load Latency in Low-Power Caches.
Proceedings of the International Symposium on Low Power Electronics
and Design (ISLPED'03). pp.
258-261.
154.
Kim, H. S., N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor,
M. J. Irwin. August 2003. Estimating Influence of Data Layout
Optimizations on SDRAM Energy Consumption.
Proceedings of the International Symposium on Low Power Electronics
and Design (ISLPED'03). pp.
40-43.
155.
Bhatkar,
A., R. Chandramouli, N. Vijaykrishnan, M. J. Irwin. July 2003.
Computation and Transmission Energy Modeling Through Profiling for MPEG4
Video Transmission. Proceedings of
the IEEE International Conference on Multimedia & Expo (ICME 2003). Volume 1, pp. 281-284.
156.
Kim, H. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2003. Adapting Instruction Level Parallelism for
Optimizing Leakage in VLIW Architectures.
Proceedings of the Workshop on Languages, Compilers, and Tools for
Embedded Systems (LCTES'03). pp.
275-283.
157.
Tsai, Y-F., D. Duarte, N.
Vijaykrishnan, M. J. Irwin. June 2003. Implications of Technology Scaling on Leakage
Reduction Techniques. Proceedings of
the Fortieth Design Automation Conference.
pp. 187-190.
158.
Schmit, H., T. Kroll, M. Khusid,
159.
Chen, G., B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R.
Chandramouli. April 2003. Energy-Aware
Compilation and Execution in Java-Enabled
160.
Gurumurthi, S., N. An, A. Sivasubramaniam, N. Vijaykrishnan, M.
Kandemir, M. J. Irwin. April 2003.
Energy and Performance Considerations in Work Partitioning for
161.
Zhang, W., M. Kandemir, N.
Vijaykrishnan, M. J. Irwin, V. De. March 2003. Compiler Support for Reducing Leakage Energy
Consumption. Proceedings of International Conference on Design Automation
and Test in
162.
Saputra, H., N. Vijaykrishnan, M. Kandemir, M.
J. Irwin, R. Brooks, S. Kim, W. Zhang.
March 2003. Masking the Energy
Behavior of DES Encryption. Proceedings
of International Conference on Design Automation and Test in
163.
Gurumurthi, S., J. Zhang, A. Sivasubramaniam, M.
Kandemir, H. Franke, N. Vijaykrishnan, M. J. Irwin. March 2003.
Interplay of Energy and Performance for Disk Arrays Running Transaction
Processing Workloads. Proceedings of
the International Symposium on Performance Analysis of Systems and Software
(ISPASS'03). pp. 123-132.
164.
Hu, J. S., N. Vijaykrishnan, M. J. Irwin, M.
Kandemir. February 2003. Using Dynamic Branch Behavior for
Power-Efficient Instruction Fetch. Proceedings
of the IEEE Annual Symposium on VLSI (ISVLSI'03). pp. 127-132.
165.
Degalahal, V.,
166.
Chen,
G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin.
November 2002.
PennBench: A Benchmark Suite for
Embedded Java. Proceedings of the
Fifth Annual IEEE Workshop on Workload Characterization (WWC'02). pp. 71-80.
167.
Zhang, W., J. S. Hu, V. Degalahal, M.
Kandemir, N. Vijaykrishnan, and M. J. Irwin. November 2002. Compiler-directed
instruction cache leakage optimization. Proceedings of the Thirty-Fifth Annual
International Symposium on Microarchitecture (MICRO-35). pp. 208-218.
168.
Li, T., L. K. John, A. Sivasubramaniam, N.
Vijaykrishnan, J. Rubio. October
2002. Understanding and Improving
Operating System Effects in Control Flow Transfer. Proceedings of the International
Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS-X).
169. &nbs p;
Charles, D., A. Hurson, N. Vijaykrishnan. October 2002.
Improving ILP with Instruction-reuse Cache Hierarchy. Proceedings of the Fifth International
Conference on Algorithms and Architectures for Parallel Processing. pp. 206-213.
170.
Zhao, J., R. Chandramouli, N. Vijaykrishnan, M. J. Irwin, B.
Kang, S. Somasundaram. September
2002. Influence of MPEG-4 Parameters on
System Energy. Proceedings of the Fifteenth Annual
IEEE International ASIC/SOC Conference. pp. 137-142.
171.
Esakkimuthu, G., N. Vijaykrishnan, M. J. Irwin. September 2002. An Analytical Power Estimation Model for
Crossbar Interconnects. Proceedings of the Fifteenth
Annual IEEE International ASIC/SOC Conference. pp.119-123.
172.
Ramanarayanan, R., N.
Vijaykrishnan, M. J. Irwin. September
2002. Characterizing Dynamic and Leakage
Power Behavior in Flip-Flops. Proceedings of the Fifteenth Annual IEEE
International ASIC/SOC Conference.
pp. 433-437.
173.
174.
Kim, S., N. Vijaykrishnan, M.
Kandemir, M. J. Irwin. September
2002. Predictive Precharging for Bitline
Leakage Energy Reduction. Proceedings of the Fifteenth Annual IEEE
International ASIC/SOC Conference. pp. 36-40.
175.
Li, L.,
176.
177.
Chen, G., M. Kandemir, N.
Vijaykrishnan, M. J. Irwin, M. Wolczko.
August
2002. Adaptive Garbage Collection for
Battery-Operated Environments. Proceedings of the Second USENIX JavaTM
Virtual Machine Research and Technology Symposium (JVM'02). pp. 1-12.
178.
De La
Luz, V., A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. June 2002. Scheduler-Based DRAM Energy Management. Proceedings of the Thirty-Ninth Design
Automation Conference (DAC). pp.
697-702.
179.
Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, W.
Zhang. June 2002. Compiler-Directed Cache Polymorphism. Proceedings of the ACM SIGPLAN Joint
Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and
Software and Compilers for Embedded Systems (SCOPES'02). pp. 165-174.
180.
Saputra, H., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H.
Hsu, U. Kremer. June 2002. Energy-Conscious Compilation Based on Voltage
Scaling. Proceedings of the ACM
SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems
(LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02). pp. 2-10.
181.
Chen,
G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, W. Wolf. May 2002. Energy Savings Through Compression in
Embedded Java Environments. Proceedings
of the ACM/SIGDA/SIGSOFT Tenth International Conference on Hardware/Software
Codesign (CODES '02). pp.163-168.
182.
Kang,
B-T., N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. May 2002.
Power Efficient Adaptive M-QAM Design Using Adaptive Pipelined Analog-to-Digital
Converter. Proceedings of the
International Conference on Acoustics, Speech and Signal Processing (ICASSP
2002). (CD ROM Proceedings).
183.
Kadayif,
184.
185.
Sivasubramaniam, A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. April 2002.
Designing Energy-Efficient Software.
Proceedings of the Next Generation Software Workshop, held in
conjunction with the International Parallel and Distributed Processing
Symposium (IPDPS 2002). p. 176.
186.
Kadayif,
187.
188.
Hu, J. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. March 2002.
Power-Efficient Trace Caches. Proceedings
of International Conference on Design Automation and Test in
189.
Kadayif,
190.
Gurumurthi, S., A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M.
Kandemir, T. Li, L. K. John. February
2002. Using Complete Machine Simulation
for Software Power Estimation: The SoftWatt Approach. Proceedings of the Eighth International
Symposium on High-Performance Computer Architecture (HPCA-8). pp. 141-150.
191.
Chen, G., R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, M.
Wolczko. February 2002. Tuning Garbage
Collection in an Embedded Java Environment.
Proceedings of the Eighth International Symposium on High-Performance
Computer Architecture (HPCA-8). pp.
92-103.
192.
Duarte, D., Y-F. Tsai, N.
Vijaykrishnan, M. J. Irwin. January 2002. Evaluating
Run-Time Techniques for Leakage Power Reduction. Proceedings of the Seventh
193.
De La Luz, V., M. Kandemir, N. Vijaykrishnan, M. J.
Irwin, A. Sivasubramaniam, I. Kolcu. January 2002.
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank
Memories. Proceedings of the Seventh
194.
Zhang, W., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D.
195.
Kirubanandan, N., A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M.
J. Irwin. December 2001. Memory Energy Characterization and
Optimization for the SPEC2000 Benchmarks.
Proceedings of the IEEE Fourth Annual Workshop on Workload Characterization
(WWC-4) (held in conjunction with MICRO-34). pp. 193-201.
196.
Kim, S.,
N. Vijaykrishnan, M. Kandemir, M. J. Irwin.
November 2001. Energy-Efficient
Instruction Cache Using Page-Based Placement.
Proceedings of the International Conference on Compilers,
Architectures and Synthesis for Embedded Systems (CASES 2001). pp. 229-237.
197.
Duarte, D., N. Vijaykrishnan,
M. J. Irwin, M. Kandemir. September 2001. Evaluating the Impact of Architectural-Level
Optimizations on Clock Power. Proceedings
of the Fourteenth Annual IEEE International ASIC/SOC Conference. pp. 447-451.
198.
Thirugnanam, G., N. Vijaykrishnan, M. J. Irwin. September 2001. A Novel Low Power
199.
Tomar, S., S. Kim, N. Vijaykrishnan, M.
Kandemir, M. J. Irwin. September 2001. Use of Local Memory for Efficient Java
Execution. Proceedings of the
International Conference on Computer Design (ICCD 2001). pp. 468-473.
200.
Kim, H. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. September 2001. A Framework for Exploring Energy-Efficient
VLIW Architectures. Proceedings of
the International Conference on Computer Design (ICCD 2001). pp. 40-45.
201.
Hezavei, J., N. Vijaykrishnan, M. J. Irwin, M. Kandemir, D.
202.
An, N., A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin,
S. Gurumurthi. September 2001. Analyzing Energy Behavior of Spatial Access
Methods for Memory-Resident Data. Proceedings
of the Twenty Seventh International Conference on Very Large Databases (VLDB
2001). pp. 411-420.
203.
Kim, S., N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin,
E. Geethanjali. August 2001. Power-aware Partitioned Cache Architectures. Proceedings of the International Symposium
on Low Power Electronics and Design (ISLPED '01). pp. 64-67.
204.
Khosla, P., H. Schmit, M. J. Irwin, N.
Vijaykrishnan, T. Cain, S. Levitan, D. Landis.
June 2001. SoC Design
Skills: Collaboration Builds a Stronger
SoC Design Team. Proceedings of the
2001 International Conference on Microelectronic Systems Education (MSE
2001). pp. 42-43.
205.
Kadayif,
206.
Kadayif,
207.
Kandemir, M., J. Ramanujam, M. J. Irwin, N.
Vijaykrishnan,
208.
Athavale,
R., N. Vijaykrishnan, M. Kandemir, M. J.
Irwin. April 2001. Influence of Array Allocation Mechanisms on
Memory System Energy. Proceedings of
the Fifteenth International Parallel and Distributed Processing Symposium
(IPDPS 2001). p. 3 (full paper on
CD-ROM).
209.
Parikh,
A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin.
April 2001. VLIW Scheduling for
Energy and Performance. Proceedings
of IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001). pp. 111-117.
210.
Vijaykrishnan,
N., M. Kandemir, S. Tomar, S. Kim, A. Sivasubramaniam, M. J. Irwin. April 2001. Energy Behavior of Java Applications from the
Memory Perspective. Proceedings of
the Java Virtual Machine Research & Technology Symposium (JVM '01). pp. 207-220.
211.
Tomar,
S., N. Vijaykrishnan, M. Kandemir, R. Shetty.
April 2001. Energy Optimization
Using Object Co-Location in Java. JOSES: Java Optimization Strategies for Embedded
Systems Workshop in conjunction with ETAPS 2001. pp. 9-15.
212.
De La Luz, V., M. Kandemir, N.
Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin.
January
2001. DRAM Energy Management Using
Software and Hardware Directed Power Mode Control. Proceedings of the Seventh International
Symposium on High Performance Computer Architecture (HPCA 2001). pp. 159-169.
213.
Duarte, N. Vijaykrishnan, M. J. Irwin, M.
Kandemir. January 2001.
Formulation and Validation of an Energy Dissipation Model for the Clock
Generation Circuitry and Distribution Networks.
Proceedings of the Fourteenth International Conference on VLSI Design. pp. 248-253.
214.
Parikh,
A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. December 2000. Instruction
Scheduling. Proceedings of the
Seventh International Conference on High Performance Computing (HiPC 2000). Springer-Verlag Lecture Notes in Computer Science 1970:335-344.
215.
Juran,
J., A. R. Hurson, N. Vijaykrishnan, S. Boonsiriwattanakul. December 2000. Data Organization and Retrieval on Parallel
Air Channels: Performance and Energy
Issues. Proceedings of the Seventh
International Conference on High Performance Computing (HiPC 2000). Springer-Verlag Lecture Notes in Computer Science 1970:501-510.
216.
De La Luz, V., M. Kandemir, N. Vijaykrishnan,
M. J. Irwin. November 2000.
Energy-Oriented Compiler Optimizations for Partitioned Memory
Architectures. Proceedings of the
Third International Conference on Compilers, Architecture and Synthesis for
Embedded Systems (CASES 2000). pp.
138-147.
217.
Kim,
H. S., M. J. Irwin, N. Vijaykrishnan, M. Kandemir. October 2000.
Effect of Compiler Optimizations on Memory Energy. Proceedings of IEEE Workshop on Signal
Processing Systems (SiPS '00). pp.
663-672.
218.
Irwin,
M. J., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam. September 2000. A Holistic Approach to System Level Energy
Optimization. Proceedings of the
Tenth International Workshop on Power and Timing Modeling, Optimization and
Simulation (PATMOS 2000).
Edited by D. Soudris,
P. Pirsch, E. Barke.
Springer-Verlag LNCS 1918:88-107.
219.
Lyuboslavsky,
V., B. Bishop, N. Vijaykrishnan, M. J. Irwin. September 2000. Design of Databus
Charge-Recovery Mechanism. Proceedings
of the International Conference on ASIC. pp. 283-287.
220.
Duarte, D., M. J. Irwin, N. Vijaykrishnan. September
2000. Modeling Energy of the Clock Generation and Distribution Circuitry. Proceedings of the International Conference
on ASIC. pp. 261-265.
221.
Athavale, R., N.
Vijaykrishnan, M. Kandemir. September
2000. Annotation Based Energy Optimization Using Array
Interleaving. Proceedings of the
Second Annual Workshop on Hardware Support for Objects and Microarchitectures
for Java. pp. 16-20.
222.
Kandemir,
M., N. Vijaykrishnan, M. J. Irwin, H. S. Kim.
August 2000. Experimental Evaluation of Energy Behavior of Iteration
Space Tiling. Proceedings of the
Thirteenth Annual Workshop on Languages and Compilers for Parallel Computing
(LCPC'00). Springer-Verlag Lecture
Notes in Computer Science 2017:142-157.
223.
Esakkimuthu,
G., N. Vijaykrishnan, M. Kandemir, M. J. Irwin.
July 2000. Memory System Energy:
Influence of Hardware-Software Optimizations. Proceedings of ISLPED'2000. pp. 244-246.
224.
Kandemir,
M., N. Vijaykrishnan, M. J. Irwin, H. S. Kim. June 2000. Towards Energy Aware Iteration Space Tiling. Proceedings
of ACM Workshop on Languages, Compilers, and Tools for Embedded Systems
(LCTES 2000). LNCS 1985, pp. 211-215.
225.
Vijaykrishnan,
N., M. Kandemir, M. J. Irwin, H. S. Kim, W. Ye. June 2000. Energy-Driven
Integrated Hardware-Software Optimization Using SimplePower. Proceedings of
the Twenty-Seventh Annual International
Symposium on Computer
Architecture (ISCA-2000). pp.
95-106.
226.
Ye,
W., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2000. The Design and Use
of SimplePower: A Cycle-Accurate Energy Estimation Tool. Proceedings of
Thirty-Seventh Design Automation Conference (DAC'00). pp. 340-345.
227.
Kandemir, M., N. Vijaykrishnan, M. J.
Irwin, W. Ye. June 2000.
Influences of Compiler Optimizations on System Power. Proceedings of
Thirty-Seventh Design Automation Conference (DAC '00). pp. 304-307.
228.
Tao,
L., L. John, N. Vijaykrishnan, A. Sivasubramaniam, A. Murthy, J. Sabarinathan.
May 2000. Using Complete System Simulation to Characterize SPECjvm98
Benchmarks. Proceedings of the
International Conference on Supercomputing (ICS '00). pp. 22-33.
229.
Parikh, A., M. Kandemir, N.
Vijaykrishnan, M. J. Irwin. April
2000. Instruction Scheduling Based on
Energy and Performance Constraints. Proceedings of the IEEE CS Annual
Workshop on VLSI (WVLSI 2000). pp. 53-58.
230.
Kim, H. S., N. Vijaykrishnan,
M. Kandemir, M. J. Irwin. April 2000.
Multiple Access Caches: Energy Implications. Proceedings of the IEEE CS Annual
Workshop on VLSI (WVLSI 2000). pp. 37-42.
231.
Hezavei,
J., N. Vijaykrishnan, M. J. Irwin. March 2000. A Comparative Study of Power
Efficient SRAM Design. Proceedings of the Tenth
232.
Radhakrishnan,
R., N. Vijaykrishnan, L. K. John, A. Sivasubramaniam. January 2000. Execution
Characteristics of Java Run-time Systems. Proceedings of the International
Symposium on High Performance Computer Architecture (HPCA-6). pp. 387-398.
233.
Irwin, M. J.,
234.
Murthy, A., N. Vijaykrishnan
and A. Sivasubramaniam. October 1999. How Can Hardware Support Just-in-Time
Compilation? Proceedings of the
Workshop on Hardware Support for Objects and Microarchitectures for Java.
pp. 15-19. (Principal author) (~67% acceptance rate)
235.
Boonsiriwattanakul, S., A. R.
Hurson, N. Vijaykrishnan, C. Chehadeh.
July-August 1999.
Energy-Efficient Indexing on Parallel Air Channels in a
236.
Vijaykrishnan, N., N.
Ranganathan. May 1999. Tuning Branch Predictors to Support Java Method Invocation. Proceedings
of the Fifth USENIX Conference on Object-Oriented Technologies and Systems (COOTS '99). pp. 217-228.
237.
Chen, R. Y., N. Vijaykrishnan,
M. J. Irwin. April 1999. Clock Power
Issues in System-on-a-Chip Designs. Proceedings of the IEEE Computer Society Annual Workshop on VLSI:
System Level Design (WVLSI '99).
pp. 48-53.
238.
Krishna, V.,
239.
Vijaykrishnan, N., N.
Ranganathan. December 1998. Object Addressing Support for a Java Processor. Proceedings of the Sixth International
Conference on Advanced Computing. pp. 61-67.
240.
Chandramouli, R., N
Vijaykrishnan,
241.
Vijaykrishnan, N., N.
Ranganathan, R. Gadekarla. July 1998. Object-Oriented Architectural Support for
a Java Processor. Proceedings of
ECOOP'98, the 12th European Conference on Object-Oriented Programming (ECOOP
'98). LNCS 1445:330-354. (Principal author)
[24 accepted out of 124 submissions] (19% acceptance rate)
242.
Ranganathan, N., N.
Vijaykrishnan, N. Bhavanishankar. October 1996. A VLSI Array Architecture with
Dynamic Clocking. Proceedings of
International Conference on Computer Design. pp. 137-140.
243.
Vijaykrishnan, N., N.
Ranganathan, N. Bhavanishankar. September 1996. DFLAP: Dynamic Frequency Linear
Array Processor. Proceedings of the
International Conference on Image Processing. pp. 2:1007-1010.
244.
Vijaykrishnan, N., R.
Chandramouli, N. Ranganathan. May 1996. Functional Reconfiguration for Fault
Tolerance: A New Approach. Proceedings of
International Conference on Modelling, Simulation and Optimization.
245.
Vijaykrishnan, N., N.
Ranganathan. January 1996. SUBGEN: A Genetic Approach for Subcircuit
Extraction. Proceedings of Ninth
International Conference on VLSI Design. pp. 343-345. (Principal author)[91 accepted out of 137
submissions] (66% acceptance rate)
246.
Venkateswaran, N.,
c. Refereed letters and other
papers.
1.
Reddy, S. S., E.,
V. Chandrasekhar, M. Sashikanth, V. Kamakoti N. Vijaykrishnan. May 2005.
A CLB Architecture for Online Correction of SEU-based Errors in LUTs of
SRAM-based FPGAs. Tenth European Test Symposium (ETS '05).
2. Reddy, S. S., E., V. Chandrasekhar, M. Sashikanth, V. Kamakoti N. Vijaykrishna