2008-present Conference Articles

On-Chip Networks

· Yanamandra, A., N. Vijaykrishnan and M. J. Irwin. Jan 2010. Optimizing Power and Performance for Reliable On-Chip Networks.  15th Asia South Pacific Design Automation Conference (ASPDAC).

· Mishra, A. K.,  R. Das, S. Eachampati, N. Vijaykrishnan, C. R. Das. Dec 2009. A Case for Dynamic Frequency Tuning in On-Chip Networks. The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO, 2009).

· Das, R., S. Eachempati, A. K. Mishra, N. Vijaykrishnan, C. R. Das.  February 2009.  Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs.  Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture (HPCA-15).  pp. 175-186.  Raleigh, NC.  (Second author supervised by candidate)

· Yanamandra, A., M. J. Irwin, N. Vijaykrishnan, M. Kandemir, S. H. K. Narayanan. January 2009.  In-Network Caching for Chip Multiprocessors. Proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2009).  Springer-Verlag LNCS 5409:373-388.  Paphos, Cyprus. 

· Park, D., S. Eachempati, R. Das, A. K Mishra, N. Vijaykrishnan, Y. Xie, C. R Das.  June 2008. MIRA: A Multi-Layered On-Chip Interconnect Router Architecture. Proceedings of the International Symposium on Computer Architecture (ISCA 2008).  pp. 251-261.  Beijing, China.  (Second author supervised by candidate)

· Das, R., A. K. Mishra, C. Nicopoulos, D. Park, N. Vijaykrishnan, R. Iyer, C. R. Das.  February 2008.  Performance and Power Optimization through Data Compression in Network-on-Chip Architectures.  Proceedings of the Fourteenth International Symposium on High Performance Computer Architecture (HPCA 2008).  pp. 215-225.  Salt Lake City, UT.  (Third author supervised by candidate)

Emerging Technologies: Nanodevices and 3D architectures

· Singh, J., K. Ramakrishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan and D. Pradhan, Jan 2010. A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application. 15th Asia South Pacific Design Automation Conference (ASPDAC).

· Saripalli, V.,S. Datta and N. Vijaykrishnan. Jan 2010. Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.  International Conference on VLSI Design, India.

· V. Saripalli, N. Vijaykrishnan and S. Datta. October 2009. Ultra Low Energy Binary Decision Diagram Circuits using Few Electron Transistors. Workshop on Nano-Bio Sensing Paradigms and Applications (in conjunction with Nanonet 2009).

· Xie, Y.,  S. Eachempati, A. Yanamandra, N. Vijaykrishnan, M. J. Irwin. July 2009. Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. IEEE/ACM International Symposium on Nanoscale Architectures. 51-56

· Al Maashri, A., G. Sun, X. Dong, V. Narayanan, Y. Xie. October 2009. 3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis. International Conference on Computer Design (ICCD).

· Sridharan, S., M. DeBole, G. Sun, Y. Xie, N. Vijaykrishnan. January 2009. A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner.  Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009).  pp. 763-768.  Yokohama, Japan.  (First two authors supervised by candidate)

· Saripalli, V, S. Mookerjea, S. Datta, N. Vijaykrishnan. November 2008. Ultra low power signal processing architectures. IEEE Biomedical Circuits and Systems Conference. pp.333-336,

· Eachempati, S., V. Saripalli, N. Vijaykrishnan, S. Datta. June 2008.  Reconfigurable BDD Based Quantum Circuits. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch 2008). pp. 61-67.  Anaheim, CA.  (First author supervised by candidate)

· Mangalagiri, P., K. Sarpatwari, A. Yanamandra, N. Vijaykrishnan, Y. Xie, M. J. Irwin, O. A. Karim.  May 2008.  A low-power Phase Change Memory Based Hybrid Cache Architecture. Proceedings of the ACM Great Lakes Symposium on VLSI  (GLSVLSI 2008).  pp. 395-398.  Orlando, FL.  (First author supervised by candidate)

Reliable Systems

· DeBole, M., R. Krishnan, V. Balakrishnan, W. Wang, L. Hong, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. January 2009.  A Framework for Estimating NBTI Degradation of Microarchitectural Components.  Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009).  pp. 455-460.  Yokohama, Japan.  (First two authors supervised by candidate)

· Henkel, J., N. Vijaykrishnan, S. Parameswaran, R. Ragel.  January 2009.  Security and Dependability of Embedded Systems:  A Computer Architects’ Perspective.  Proceedings of the Twenty-Second International Conference on VLSI Design (VLSI Design 2009).  pp. 30-32.  New Delhi, India.

· Ramakrishnan, K., N. Vijaykrishnan, Y. Xie.  October 2008.  Comparative Analysis of NBTI Effects on Low Power and High Performance Flip-Flops. Proceedings of the XXVI International Conference on Computer Design (ICCD 2008).  pp. 200-208.  Lake Tahoe, CA.  (First author supervised by candidate)

· Soundarajan, N., N. Vijaykrishnan, A. Sivasubramaniam. August 2008.  Impact of DVFS on the Architectural Vulnerability of GALS Architctures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2008).  pp. 351-356.  Bangalore, India.

· Soundararajan, N., A. Yanamandra, C. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin.  June 2008.  Analysis and Solutions to Issue Queue Process Variation.  Proceedings of the Thirty-Eighth Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2008).  pp. 11-21.  Anchorage, Alaska.  (Third author supervised by candidate)

· Krishnan, R., R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, K. Unlu.  March 2008. Hierarchical Soft Error Estimation Tool (HSEET).  Proceedings of the Ninth International Symposium on Quality Electronic Design (ISQED 2008).  pp. 680-683.  San Jose, CA.  (First author supervised and second author co-supervised by candidate)

· Atienza, D., G. De Micheli, L. Benini, J. L. Ayala, P. G. Del Valle, M. DeBole, N. Vijaykrishnan. January 2008.  Reliability-Aware Design for Nanometer-Scale Devices.  Proceedings of the Thirteenth IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2008).  pp. 549-554. Seoul, Korea.  (Sixth author supervised by candidate)

Reconfigurable and Embedded Computing

· Kim, J.S., C-L Yu,  L. Deng,  S. Kestur,  V. Narayanan,  C. Chakrabarti. October 2009. FPGA Architecture for 2D Fast Fourier Transform Based on 2D Decomposition for Large-Sized Data. IEEE Workshop on Signal Processing Systems.

· Bae, S., R. Krishnan, N. Vijaykrishnan. A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. IEEE Computer Society Annual Symposium on VLSI, pp.193-198,

· Mangalagiri, P., N. Vijaykrishnan, May 2009. Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. IEEE Computer Society Annual Symposium on VLSI, pp.61-66.

· Bae, S., P. Mangalagiri, N. Vijaykrishnan.  April 2009.  Exploiting Clock  Skew Scheduling for FPGA.  Proceedings of the Design Automation & Test in Europe (DATE 2009). Nice, France.  (First two authors supervised by candidate)

· Mangalagiri, P., S. Bae, R. Krishnan, N. Vijaykrishnan, Y. Xie, T. Tuan. November 2008.  Thermal-Aware Reliability Analysis for Platform FPGAs. Proceedings of the International Conference on Computer Aided Design (ICCAD 2008).  pp. 722-727.  San Jose, CA.  (First three authors supervised by candidate)

· Deng, L., C-L. Yu, C. Chakrabarti, J. Kim, N. Vijaykrishnan.  October 2008.  Efficient Image Reconstruction Using Partial 2D Fourier Transform. Proceedings of the 2008 IEEE Workshop on Signal Processing Systems (SIPS 2008). pp. 49-54.  Washington, D.C.

· Irick, K., N. Vijaykrishnan, M. DeBole, A. Gayasen. April 2008.  A Hardware Efficient Support Vector Machine Architecture for FPGA. Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008). pp. 304-305.  Stanford, CA.  (First and third authors supervised and fourth author co-supervised by candidate)