Research News

11/2014 The co-authored paper "Overcoming the Challenges of Cross-Point Resistive Memory Architecture" is accepted by HPCA'15, which will be hosted in Bay Area, California, Feb. 7-11, 2015
09/2014 The co-authored paper "NVMain 2.0: A User-friendly Memory Simulator to Model (Non-)Volatile Memory Systems" is accepted by Computer Architecture Letters (CAL). This is the first paper in the group that will appear in CAL!
09/2014 The co-authored paper "Using Multi-Level Cell STT-RAM for Fast and Energy-Efficient Local Checkpointing" won ICCAD'14 Best Paper Award (front-end)!!
06/2014 Give one talk about memory modelling in the tutorial on ISCA
05/2014 The paper "3D-SWIFT: A High-Performance 3D-Stacked Wide IO DRAM" won GLSVLSI'14 Best Paper Award!!
03/2014 Successfully pass the Ph.D. defense.
02/2014 The paper "Half-DRAM: A High-bandwidth and Low-power DRAM System from the Rethinking of Fine-grained Activation" is accepted by ISCA'14!
11/2013 The paper "CREAM: A Concurrent-Refresh-Aware DRAM Memory System" is accepted by HPCA'14!
05/2013 The simulator NVMain2.0 is released. This is a cycle-accurate simulator for both DRAM and NVMs. Matt is the father of this simulator. I redesign the memory timing model and add the support for fine-grained structure.
04/2012 Release DRAMSim2 patch for Gem5's Ruby. Sorry, the patch is not available anymore. Please wait for our new memory simulator!
12/2011 Successfully pass the Comprehensive Exam.
01/2011 Work in Sensing and Energy Research Group (SERG) in the Microsoft Research for a low-power GPS.
09/2010 The talk "A 5-layer 3D Stacked Chip Prototyping for H.264 Application" won Best in Session Award in SRC's annual event TECHCON!!
07/2010 Intership in ITRI, Taiwan for a 3D embedded on-chip interconnect design. Btw, enjoy the amazing food as well!
11/2009 Relocate to Peking University and work with MPRC colleagues for a 3D chip tapeout. The chip has 5-layers (2 logic layers and 3 DRAM layers) and leverages TSVs as the vertical connection. The 3D DRAM is from Tezzaron.
09/2009 Successfully pass the Candidacy Exam.
02/2009 It is the first time to attend a computer architecture conference HPCA in Raleigh, North Carolina.
01/2009 Implement an AHB interface in Leon3 so that it can read out the shadow registers in the SPARC processor. The register value is further read out via UDP. This function is integrated into Jin Ouyang's Checkercore project.
08/2008 Start Ph.D. program at Penn State.