Niranjan Soundararajan
Email: soundara [at] cse [dot] psu [dot] edu
Ph.D Candidate [ CV ]
Education
Fall 2005 - Present. Ph.D candidate,
Computer Science and Engineering.
Pennsylvania
State University, University Park.
Advisors: Dr. Anand Sivasubramaniam, Dr. Vijaykrishnan Narayanan
B. E
in Computer Science and Engineering (2000 - 2004)
Sri Venkateswara College of Engg,
University of Madras, Chennai, TN, India
Advisor: Prof. Nagarajan Venkateswaran
Research Interests
My primary area of research is Computer Architecture,
specifically Reliability and
Fault-Tolerant Computing in Single and Multicores.
Besides reliability, I have my interests in the following
areas as well.
-
On-chip Interconnection networks for scalable
multicore designs
- Hybrid
on-chip memory design
- Cache
coherency protocols in many-core era
- Transactional
Memory
RESEARCH SUMMARY
My doctoral work involves developing architectural-level
techniques to address the increasing impact of different reliability phenomena in
performance-critical pipeline components (Reservation stations, Reorder
Buffers) in single and multicores.
Transistor failures occur early in their lifetime due to
manufacturing defects or due to wearout towards the
end of lifetime or random faults occur in between. Each of these phenomena has
a different cause and, importantly, a differing impact on the underlying
hardware. Given the increase failure rates, it is critical to provide solutions
addressing their impact. A low performance overhead is equally critical to make
adoption of these techniques viable for products available in the market. My Ph.d, hence, targets architectural designs involving
low-cost, low-overhead solutions that address reliability phenomena affecting
current and future generation microprocessors.
My
CV includes a detailed summary describing the different projects that are part
of my thesis in greater detail.
Publications
1.
Optimizing Power and Performance for Reliable On-Chip
Networks. Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan
Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan. To
Appear in 15th Asia and South Pacific Design Automation Conference (ASP-DAC), January
2010
2.
Quantized AVF: A Means of
Capturing Vulnerability Variations over Small Windows of Time. Arijit Biswas,
Niranjan Soundararajan,
Shubu Mukherjee, Sudhanva Gurumurthi. IEEE Workshop
on System Effects of Logic Soft Errors (SELSE-5), March 2009. [PDF]
3. Impact of DVFS on the architectural
vulnerability of GALS architectures. Niranjan
Soundararajan, Vijaykrishnan
Narayanan, Anand Sivasubramaniam.
Proceedings of the International Symposium on Low Power Electronics and
Design (ISLPED), August 2008. [PDF]
4. Analysis and solutions to Issue Queue Process
Variations. Niranjan Soundararajan, Aditya Yanamandra,
Chrysostomos Nicopolous, Vijaykrishnan Narayanan, Anand Sivasubramaniam, Mary Irwin. Proceedings of 38th Annual
IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2008. [PDF]
5.
Mechanisms
for bounding vulnerabilities of processor structures. Niranjan Soundararajan, Angshuman Parashar,
Anand Sivasubramaniam. Proceedings
of the 34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [PDF]
6.
PASCOM:
Power Model for Supercomputers. Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan
Soundararajan. Architecture of
Computing Systems (ARCS), March
2006.
7. Fault Tolerant Memory In Processor - SuperComputer On a Chip. Niranjan Soundararajan, Arrvindh Shriraman. Poster Presentation: MAPLD International Conference, September 2005.
8.
Memory
In Processor SuperComputer On
a Chip - Processor Design and Execution Semantics for Massive On-Chip
Parallelism. Prof. N. Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan, Workshop on Massively Parallel
Processing (WMPP) held in conjunction with IPDPS, April 2005.
9.
Memory
In Processor: A Novel Design Paradigm for
Supercomputing Architectures. Prof. N. Venkateswaran, Aditya Krishnan, Arrvindh Shriraman, S. Niranjan Kumar, S.
Srinivas, ACM SIGARCH Computer Architecture News (CAN), June 2004.
10. The MIP Project: Evolution of a Novel Supercomputer Architecture. Prof. N. Venkateswaran, Arrvindh Shriraman, Aditya Krishnan, S. Niranjan Kumar, S. Srinivas. MEmory performance: DEaling with Applications (MEDEA) Systems and Architecture Workshop held in conjunction with PACT, September 2003.
InternSHIP Experience
Interned
(Co-op) with FACT group in Intel, MA
over Summer-Fall 2007.
Patents
Detecting Architectural
Vulnerability of Processor Structures. Arijit Biswas, Niranjan Soundararajan, Shubu Mukherjee. Applied April 2008.
Courses
Operating
Systems Design, Programming Language Concepts, Self-* Systems, Computer
Networks, Virtual Machines
Interconnection
networks (related to NOCs), Multiprocessor Architecture, Compiler Construction,
Topics in Computer Architecture, Storage Systems