I am a PhD Candidate in the Department of Computer Science and Engineering at Penn State University, where I am a member of the High Perfomance Computer Lab. I joined Penn State in fall 2005. Prior to that I was working at STMicroelectionics Ltd . I did my undergraduation in India from NIT, Rourkela (2000-2004). I am currently advised by professor Chita Das. I have also been mentored by professors Vijay Narayanan and Yuan Xie at Penn State.

I interned at Intel, Hardware Architecture Lab (CTG-STL-HAL) for two lovely summers (2006 & 2007) at Hillsboro, Oregon. Here I developed simulation tools and worked on Platform QoS, Flash Memory Architectures with Jaideep Moses. I continued to work with Ravi Iyer from my research group at Intel on exploring compression in On-Chip Networks. In summer 2008, I enjoyed working with Onur Mutlu and Thomas Moscibroda at Microsoft research, Redmond, Washington. We are continuing our work towards fair and application aware on-chip networks.

12/2009 : I am planning to graduate in Spring 2010. I am looking for academic and industry research positions.

7/2009 : Our paper on Application-Aware Prioritization Mechanisms for NoCs accepted in MICRO-42.

7/2009 : Our paper on Dynamic Frequency Tuning for NoCs accepted in MICRO-42.

6/2009 : Our paper on CMP resource partitioning accepted in SC '09.

5/2009 : I will be attending Grace Hopper Celebration of Women in Computing, 2009.

4/2009 : I received the CSE Outstanding Graduate Research Assitantship Award for year 2008.

3/2009 : I passed my thesis proposal and comprehensive examination.

11/2008 : I will be teaching undergraduate course "Computer Organization and Design", CSE 331 this spring

10/2008 : Our paper on on-chip network topologies got accepted in HPCA-15