Hi! I am Prasanna Rengasamy.
I am a 5th year PhD candidate at the Computer Systems Lab at Penn State. I am interested in studying and optimizing the architecture and system performance of handheld devices.
My current research involves system level optimizations for improving the performance, power and energy efficiency of handheld app executions. We recently characterized the contrasts in execution characteristics of desktop and server class benchmarks vs mobile apps to propose a software optimization for representing Critical Instruction Chains as 16-bit Thumb instructions. Read more...
I am advised by Prof Anand Sivasubramaniam. I also work with Prof Mahmut Kandemir and Prof Chita Das.
You can reach me at pur128-at-cse-dot-psu-dot-edu.
CritICs Critiquing Criticality in Mobile Apps
Prasanna Venkatesh Rengasamy, Haibo Zhang, Shulin Zhao, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut Kandemir, Chita Das
To Appear In Proceedings of The 51st Annual IEEE/ACM International Symposium on Microarchitecture,
Fukuoka, Japan. October 2018.
Acceptance ratio: 74/351 (21%)
FLOSS: FLOw Sensitive Scheduling on Mobile Platforms
Haibo Zhang, Prasanna Venkatesh Rengasamy, Nachiappan Chidambaram Nachiappan, Shulin Zhao, Anand Sivasubramaniam, Mahmut Kandemir, Chita Das
To Appear In Proceedings of The Design Automation Conference,
San Francisco, CA. 2018.
Acceptance ratio: 180/674 (26.7%)
Race-To-Sleep + Content Caching + Display Caching: A Recipe for Energy-efficient Video Streaming on Handhelds
Haibo Zhang, Prasanna Venkatesh Rengasamy, Shulin Zhao, Nachiappan Chidambaram Nachiappan, Anand Sivasubramaniam, Mahmut Kandemir, Chita Das, Ravi Iyer
In Proceedings of The 50th Annual IEEE/ACM International Symposium on Microarchitecture,
Boston, MA. October 2017.
Acceptance ratio: 61/327 (18.7%)
Characterizing Diverse Handheld Apps for Customized Hardware Acceleration
Prasanna Venkatesh Rengasamy, Haibo Zhang, Nachiappan Chidhambaram Nachiappan, Shulin Zhao, Anand Sivasubramaniam, Mahmut Kandemir, Chita R Das
In Proceedings of IEEE International Symposium on Workload Characterization, Seattle WA. October 2017.
Acceptance ratio: 23/83 (27.7%)
Instruction and Logic for Managing Cumulative System Bandwidth through Dynamic Request Partitioning
Jayesh Gaur, Prasanna Rengasamy, Pradeep Ramachandran, Sreenivas Subramoney
U.S Patent No. 20160179387, 14/971,057, 2016.
Implemented from Intel Skylake (6th Gen) hardware chips
Exploiting staleness for approximating loads on CMPs
Prasanna Venkatesh Rengasamy, Anand Sivasubramaniam, Mahmut T Kandemir, Chita R Das
In Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), San Francisco, October 2015.
Acceptance ratio: 39/179 (21.8%)
Using Packet Information For Efficient Communication In NoCs
Prasanna Venkatesh Rengasamy, Madhu Mutyam
In Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Ferrara, Italy, September 2014.
Acceptance ratio: (26%)
Prevention slot flow-control mechanism for low latency torus network-on-chip
Arpit Joshi, Prasanna Venkatesh, Madhu Mutyam
In Proceedings of the IET Computers & Digital Techniques, Vol 7, Issue 6, Pages 304-316, November 2013.
Over the past 10 years, I had the good fortune to work with diverse people from 7 research labs both as a developer and a researcher.
|High Performance Computing Lab, Penn State||2015-present||PhD Candidate|
|Intel Strategic CAD Labs, Hillsboro, OR||2015||Research Intern|
|Computer Systems Lab, Penn State||2014-present||PhD Candidate|
|Intel Client CPU Performance & Power Architecture Team, Bangalore, India ||2014||Research Intern|
|PACE Lab, IIT Madras, India||2011-2014||MS Scholar, Junior Research Fellow|
|TCS Infrastructure Lab, Chennai, India||2010-2011||Researcher - R & D|
|Kloster Labor Fur Cytolgie, Soest, NWF, Germany||2008-2009||Intern Developer|
My linkedin and google scholar pages are up-to-date. To know more about me, please find my vita here:
I am currently maintaining our lab's website:
CSL Website(filters to my name)
I have TA-ed one semester in my Ph D (so far) and two semesters in my MS.
| CSE473 Operating Systems, Penn State|| Fall 2014|
| CS4100 Computer System Design, IIT Madras ||Fall 2013|
| CS6560 Parallel Computer Architecture, IIT Madras |
Outstanding TA Award
I have also helped and managed the TAs for CSE473 in Fall 2016 and CSE 511 (Grad level OS) in Fall 2017.