CMPEN 411 VLSI Digital Circuits
Instructor: Kyusun Choi
|| 112F IST Building
|| 863-1268 or 865-9505
| Office Hours:
|| 2:30pm - 4:00pm Tue.
|| 2:30pm - 4:00pm Wed.
Teaching Assistant: Sumitha George
|| 338E IST Building
| Office Hours:
|| 3:30pm - 5:00pm Mon.
|| 3:30pm - 5:00pm Fri.
- CSE Lab: Room 218 IST Building, UNIX
- Remote Access: Student with his/her own Windows PC or laptop
- Remote Access: Room 109 Willard, Room 107 Waring, Room 108 Waring, and Room 201 Pollock
- Remote Access: Engineering computer lab in Hammond?
Digital Integrated Circuits: A Design Perspective, 2nd Ed.,
J. M. Rabaey, A. Chandrakasan, B. Nikolic, Prentice Hall, 2003.
CMPEN 411 Web Page:
CMOS VLSI Design, A Circuit and Systems Perspective, 3rd Ed.,
N. H. E. Weste, D. Harris, Addison Wesley, 2005
CMOS: Circuit Design, Layout, and Simulation, 3rd Ed.,
R. Jacob Baker, Wiley-IEEE, 2010
- Timely information such as announcements, homeworks, projects,
and exams will be posted and updated.
- Each student designs a small size chip throughout the
semester. Among the best completed chip designs, a few designs
will be selected and fabricated through the MOSIS Education
program (depends on MOSIS approval). Student who's project
will be fabricated must take a follow up one credit independent
study course on the subsequent semester to test the fabricated chip.
- There will be two mid-term exams and one comprehensive final exam. Two
mid-term dates are listed below. The final exam schedule will be announced in
elion. One may use the textbooks during an exam if they are kept free of any
writings or annotations. Make-up exam will only be administered if you
have received prior approval from the instructor at least one week before the
regular exam is scheduled, or if a last minute emergency or illness occurs. In
the case of emergencies or illnesses you should, if possible, contact the
instructor or call the main CSE office (865-9505) and leave a message indicating
that you will not be able to take the exam as scheduled and why. Regardless
of your circumstances, approval to take a make-up exam is up to the
||Sep. 22, 2016, 8:15pm - 9:50pm, at Room ?? Willard Building|
||Oct. 27, 2016, 8:15pm - 9:50pm, at Room ?? Willard Building|
||Date, time, and place to be announced, elion|
- Approximately eleven homework/project assignments will be given during the semester.
Late homework/project will not be accepted. However, one homework/project grade (lowest
one) will be dropped. Homework/project are to be completed as
an individual effort.
- Approximately eleven pop quizzes will be given during the semester. Missed
quiz can not be remade. However, one quiz grade (lowest one) will be
Tentative Course Outline:
- Learn digital integrated circuit design, layout, simulation, and
fabrication; VLSI design techniques and system architecture;
computer-aided design tools and techniques
Topic (textbook reading)
1 Introduction (ch 1.1 - 1.2)
2 Design metrics (ch 1.3)
3 The MOS transistor (ch 3.1 - 3.3.2)
4 The CMOS inverter - a static view (ch 5.1 - 5.3)
5 IC manufacturing; design rules (ch 2.1 - 2.3)
6 Static CMOS logic (ch 6.1 - 6.2.1)
7 Pass transistor logic (ch 6.2.3)
8 Capacitance effects (ch 3.3.3 - 3.3.4)
9 Resistance effects and wire models (ch 4.1 - 4.5.2)
10 The CMOS inverter - a dynamic view (ch 5.4.1 - 5.4.2)
11 Designing fast logic (ch 5.4.3; 9.2.2; 9.3.3)
12 Designing energy efficient logic (ch 5.5)
13 Designing energy efficient logic 2 (ch 5.5)
14 Dynamic CMOS logic (ch 6.3 - 6.4)
15 Dynamic CMOS logic (ch 6.3 - 6.4)
16 Timing metrics; static sequential circuits (ch 7.1 - 7.2)
17 Dynamic sequential circuits (ch 7.3; 7.5)
18 Timing issues; datapath design (ch 7.7; 10.1 - 10.3.3; 11.1 - 11.2)
19 Adders (ch 11.3)
20 Multipliers (ch 11.4)
21 Shifters, big decoders, big multiplexors (ch 11.5 - 11.6)
22 Semiconductor memories; ROM cores (ch 12.1 - 12.2.1)
23 SRAM, DRAM, and CAM cores (ch 12.2.2 - 12.2.4)
24 Peripheral memory circuitry (ch 12.3)
25 Power (ch 11.7; 12.5)
26 Design flow (ch 9.1 - 9.3)
27 Technology trends
28 Emerging technology