A picture of me, possibly qualifying as recent.

John (Jack) Sampson

Assistant Professor

Dorothy Quiggle Faculty Development Assistant Professorship

Contact information:
Email - [lastname]@cse.psu.edu
Office - W324 Westgate Building
    University Park, PA 16802
Phone - Ext. 57496
CSE Department, School of EECS, College of Engineering, PSU


My primary research interests lie broadly in the area of computer architecture, with energy-efficiency of one form or another being the thread that ties together much of my work since the mid-2000s. I've recently been focusing on how to extend notions of dark-silicon management developed for the processor core to the other "uncore" components of a modern processor/SoC (caches, memory controllers, accelerators, memory, storage), investigating systems constrained by the meager and unpredictable power budgets of energy-harvesting, and augmenting traditional processing elements with accelerators that leverage emerging device technologies to "let the physics do the computing."

As part of the Microsystems Design Lab in the School of EECS, I have ongoing research collaborations with members of both the EE and CSE departments. While at Penn State, it has been my privilege to actively collaborate with both faculty and students working on the "Visual Cortex on Silicon" NSF expedition. While computer vision itself is an area I would still claim to have quite modest expertise in, developing hardware approaches to support computer vision tasks aligns naturally with my interests in energy-efficient computing and constructing clean abstractions for accelerator-rich architectures.


Current PhD Advisees

  • Minli (Julie) Liao (Joined Fall 2015)
  • Saambhavi Baskaran (Joined Fall 2016)
  • Zhixuan Huan (Joined Fall 2016)

Graduated Students

  • Kaisheng Ma (Defended 2017, Dissertation Pending)
    • - Co-advised with Vijay Narayanan

  • Wei-Yu (William) Tsai (PhD 2017)
    • - Co-advised with Vijay Narayanan

  • Nandhini Chandramoorthy (PhD 2016)
    • - Co-advised with Vijay Narayanan
    • - 1st placement: IBM Watson

  • Siddharth Advani (PhD 2016)
    • - Co-advised with Vijay Narayanan
    • - 1st Placement: Samsung Research America (Dallas)

  • Ivan Stalev (MS 2015)
    • - 1st Placement: Lyft



  • ASKS: Architecture Support for darK Silicon (2014-)
      Successfully navigating the post-Dennardian landscape of computer engineering requires drawing on diverse sets of expertise ranging from low-power circuit design to the ability to integrate and exploit emerging technologies and techniques into both traditional and less traditional multiprocessor designs. Our work aims to tackle the following challenges:
      1) Explore the relationship between the design of uncore components and continuing dark/dim silicon trends
      2) Co-manage the bandwidth opportunities and thermal challenges introduced by 3D stacking
      3)Exploit power and energy efficiency opportunities provided by non- volatile storage while maintaining traditional semantics
      4) Perform cross-layer optimizations in the face of dark silicon challenges that span from within a given processor's datapaths to memory and storage sub-systems shared among multiple processors.
    • [C/19]
    • [Ci/7]
    • [J/3]

  • Energy-efficient Computer Vision Processing (2014-)
      This area consists of collaborations with the members of the Visual Cortex on Silicon Expedition that focus on the energy-efficiency aspects of intelligently utilizing context information and effectively deploying computer vision accelerators.
    • [Ci/4]
    • [W/3]
    • [C/23]

  • Energy-harvesting Batteryless Non-volatile Processors (2014-)
      In a batteryless, energy-harvesting environment, as may become a common case for health wearables and other IoT devices, power interruptions can occur more frequently than traditional processors are likely to complete a single work unit. In such an environment, non-volatile storage of the processor state, down to the microarchitectural level, must be deeply integrated into the pipeline in order to ensure forward progress. We are exploring the various opportunities to tune the microarchitectures and power management policies of these devices and highlighting where they are both similar to and distinct from battery-powered deployments and validating our assumptions with prototype NVP platformss produced by our collaborators.
    • [C/24]
    • [Ci/6]
    • [J/4]

  • Exploiting Emerging Device Features for Novel Processing Opportunities (2013-)
      Emerging devices, from contenders for the post-CMOS crown, such as TFETs, to more niche-oriented computing devices, such as nano-oscillators and multi-input NEMS, all offer unique tradeoffs. In some cases, the physics of the device can perform a computation directly. In others, device limitations, such as low maximum frequency, can be turned into strengths (deeper 3D stacking before hitting thermal limits) at the system level. In all cases, new devices bring new opportunities to use the right device for the right task to maximize energy-efficiency.
    • [C/18]
    • [C/26]

Completed, Inactive, or External

  • Conservation Cores / GreenDroid (2007-2014)
      The C-Cores project developed an automated C-to-silicon infrastructure for generating specialized hardware (Conservation Cores) to improve the energy efficiency of mature codebases and for integration of these Conservation Cores into a multiprocessor platform. Work continued on a prototype mobile application processor called GreenDroid that leveraged dark silicon to dramatically reduce energy consumption compared to contemporary smart phones. GreenDroid incorporates many specialized processors (Conservation Cores) targeting key portions of Google's Android smart phone platform to reduce their energy consumption.
    • [TR/1]
    • [C/7]
    • [C/8]
    • [TR/2]
    • [C/9]
    • [TR/3]
    • [J/1]
    • [C/10]
    • [C/11]
    • [C/12]
    • [W/2]
    • [J/2]

  • Data Center Power Management (2011-2012)
      This work explored power management policies governing the use of stored energy to constrain peak power consumption in data centers and plausible strategies for deploying the necessary distributed energy storage.
    • [TR/4]
    • [C/13]

  • Introspectively Tracking Program Execution Progress and Interference (2011-2013)
      Both hardware-assisted and pure software (performance-counter driven) approaches and mechanisms were investigated for accurately estimating what the interference-free performance of a dynamically executing program would have been. Key applications for the techniques include augmenting job scheduling and metering in IaaS environments.
    • [C/14]
    • [C/16]

  • Program Phase Analysis (2004-2006)
      Work in this area included extensions of SimPoint to x86, effective methods for mapping program counter statistics to phase information, and suite-level phase sampling.
    • [C/1]
    • [C/2]
    • [C/3]

  • "Potpourri"
    • Filter Barriers (2005-2006):[W/1] [C/6] [P/1]
    • Hardware Support for Transactional Memory (2005-2007):[C/4]
    • Quantifying the Marginal Value of Microarchitectural Heterogeneity (2013-2014)
    • Vector Acceleration for Energy-Efficiency: (2005-2006):[C/5]

Research Sponsors

  • NSF/SRC E2CDA: 2D Electrostrictive FETs for Ultra-Low Power Circuits and Architectures. 2016-2019
  • Intel: A Configurable Vision Platform for Cognitive Image Analytics. 2015-2018
  • NSF: CCF: SHF: Medium: ASKS - Architecture Support for darK Silicon. 2014-2018