- PhD student in Department of Computer Science and Engineering,
The Pennsylvania State University
- MS in Department of Computer Science and Information Engineering,
National Taiwan University
- BEd in Department of Information Computer Education
National Taiwan Normail University
I am currently a PhD student in Department of Computer Science and
Engineering, The Pennsylvania State University.
My advisor is Dr.
Vijaykrishnan Narayanan.
Contact Info
- 351 IST Building, University Park, PA 16802
- TEL:+1-814-863-1047
- Email: ilin at cse_dot_psu_dot_edu
Research Interest
- Electronic Design Automation
- VLSI
- SoC
Publications
- I.-C. Lin and V. Narayanan, "System Level Power and Reliability
Modeling," Ph.D. Forum, Design, Automation and Test in Europe Conference
and Exhibition, Apr. 2007 (DATE '07)
- N. Dhanwada, R. Bergamaschi2, W. Dungan, I. Nair, P. Gramann, W.
Dougherty1 and I.-C. Lin, "Transaction-Level Modeling for Architectural
and Power Analysis of PowerPC and CoreConnect based Systems," in Journal
of Design Automation for Embedded Systems (JDAES '06)
- I.-C. Lin, S. Srinivasan, V. Narayanan, N. Dhanwada, "Transaction Level
Error Susceptibility Model for Bus Based SoC Architectures," in
Proceeding of International Symposium on Quality Electronic Design, Mar.
2006 (ISQED '06)
- I.-C. Lin and V. Narayanan, "Transaction Level Power Modeling for PCI
Express," in TECHCON, Oct. 2005 (TECHCON '05)
- N. Dhanwada, I.-C. Lin and V. Narayanan, "A Power Estimation Methodology
for SystemC Transaction Level Models," in Proceeding of International
Conference on Hardware/Software Codesign and System Synthesis, Sep. 2005
(CODES+ISSS '05)
- N. Dhanwada, R. Bergamaschi, W. Dungan, I. Nair, W. Dougherty, Y. Shin,
S. Bhattacharya, I. Lin, J. Darringer, S. Paliwa1, "Simultaneous
Exploration of Power, Physical Design and Architectural Performance
Dimensions of the SoC Design Space using SEAS", in IP Based SoC Design
Forum & Exhibition, Dec 2004 (IP/REUSE 04 )
Link
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