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Hsiang-Yun Cheng
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I received my bachelor's and master's degrees from Department of Computer Science and Information Engineering, National Taiwan University, in 2007 and 2010. Now, I am a second year Ph.D. student
in Department of Computer
Science and Engineering, Penn State
University. I'm a member
of MDL group in
PSU, and my advisor is
Professor Yuan
Xie.
My research interests include memory system design for future multi/many-core architectures, architectural exploration of new memory technologies, and three-dimensional (3D) architecture.
My Curriculum Vitae is available here.
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Education
| 2010 - present |
PhD., Department of Computer Science and Engineering, PSU |
| 2007-2010 |
M.S., Department of Computer Science and Information Engineering, National Taiwan University |
| 2003-2007 |
B.S., Department of Computer Science and Information Engineering, National Taiwan University |
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Teaching
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Publications
- Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang,
Memory Latency Reduction via Thread Throttling. In Proceedings of ACM/IEEE International Symposium on Microarchitecture (MICRO),
2010.
- Hsiang-Yun Cheng, Jian Li, Chia-Lin Yang,
An Analytical Model to Exploit Memory Task Scheduling. In Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture (INTERACT-14), held in conjunction with ASPLOS, 2010.
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Experiences
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Courses
CSE597D Topics in Computer Hardware Design
CSE565 Algorithm Design and Analysis
CSE521 Compiler Construction
CSE532 Multiprocessor Architecture
CMPEN411 VLSI Digital Circuits
CSE530 Fundamentals of Computer Architecture
CSE514 Comhputer Networks
CSE517 Performance Evaluation
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