F. Li, G. Chen, M. Kandemir, and I. Kolcu. Profile-Driven Energy Reduction in Network-on-Chips. To appear in Proc. Conference on Programming Language Design and Implementation (PLDI'07), San Diego, June 2007.
F. Li, C. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan and M. Kandemir. Design and Management of 3D Chip Multiprocessors using Network in-Memory. In Proc. the 33rd Annual International Symposium on Computer Architecture (ISCA'06), Boston, USA, June 2006 [pdf]
G. Chen, F. Li, M. Kandemir, and M. J. Irwin. Reducing NoC Energy Consumption Through Compiler-Directed Channel Voltage Scaling. In Proc. Conference on Programming Language Design and Implementation (PLDI'06), Ottawa, Canada, June 2006.
M. Mutyam, F. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin. Compiler-Directed Thermal Management for VLIW Functional Units. In Proc. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Canada, June 2006.
F. Li, M. Kandemir and I. Kolcu. Exploiting Software Pipelining for Network-on-Chip architectures. In Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'06), Karlsruhe, Germany, March 2006. [pdf]
G. Chen, F. Li, and M. Kandemir. Compiler-directed Channel Allocation for Saving Power in On-chip Networks. In Proc. Symposium on Principle of Programming Languages (POPL'06), Charleston, SC, January 2006.
M. Kandemir, G. Chen and F. Li. Maximizing Data Reuse for Minimizing Memory Space Requirements and Execution Cycles. In Proc. the 11th Asia and South Pacific Design Automation Conference (ASP-DAC'06), Yokohama, Japan, January 2006.
F. Li, G. Chen and M. Kandemir. Compiler-Directed Voltage Scaling on Communication Links for Reducing Power Consumption. In Proc. International Conference on Computer Aided Design (ICCAD'05), San Jose, CA, November 2005. [pdf]
F. Li, G. Chen, M. Kandemir and M. J. Irwin. Compiler-Directed Proactive Power Management for Networks. In Proc. International Conference on Compiler, Architecture and Synthesis for Embedded Systems (CASES'05), San Francisco, CA, September 2005. [pdf]
F. Li, G. Chen, M. Kandemir and M. Karakoy. Exploiting last idle periods of links for network power management. In Proc. the 5th ACM international conference on Embedded software (EMSOFT '05), Jersey City, NJ, September 2005. [pdf]
F. Li and M. Kandemir. Locality-conscious workload assignment for array-based computations in MPSOC architectures. In Proc. Design Automation Conference (DAC'05), Anaheim, CA, June 2005 (Best Paper Nomination). [pdf]
F. Li and M. Kandemir. Increasing data TLB resilience to transient errors. In Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'05), Tampa, Florida, May 2005.
F. Li, M. Kandemir, R. Brooks and G. Chen. A Compiler-Based Approach to Data Security. In Proc. International Conference on Compiler Construction, Edinburgh, Scotland, April, 2005.
M. Kandemir, F. Li, G. Chen, G. Chen and O. Ozturk. Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing. In Proc. Design, Automation and Test in Europe (DATE'05), Munich, Germany, March, 2005. [pdf]
J. S. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan and M. J. Irwin. Compiler-Directed Instruction Duplication for Soft Error Detection. In Proc. Design, Automation and Test in Europe (DATE'05), Munich, Germany, March, 2005. [pdf]
G. Chen, F. Li, M. Kandemir, and I. Demirkiran. Increasing FPGA resilience against soft errors using task duplication. In Proc. the Asia and South Pacific Design Automation Conference (ASPDAC'05), Shanghai, China, January 2005.
F. Li, P. Agrawal, G. Eberhardt, E. Manavoglu, S. Ugurel, and M. Kandemir. Improving memory performance of embedded Java applications by dynamic layout modifications. In Proc. the 6th International Workshop on Java for Parallel and Distributed Computing, in conjunction with IPDPS'04, Santa Fe, New Mexico, April 26, 2004.
F. Li and M. Kandemir. Improving performance of Java applications using a coprocessor. In Proc. the Thirteenth International Heterogeneous Computing Workshop (HCW'04), in conjunction with IPDPS'04, Santa Fe, New Mexico, April 26, 2004.
Teaching
Fall 2006, CSE331: Computer Organization and Design (Instructor)
Fall 2003, CSE477: VLSI digital circuits
Spring 2003, CSE471: Logical Design of Digital Systems
Fall 2002, CSE271: Introduction to Digital Systems
Working Experiences
05/2006 – 08/2006
Summer Internship at NVIDIA, Santa Clara, CA, USA