Paul Falkenstern
Research and Academics

I am entering my fifth year here at PSU, studying Computer Engineering. I'm enrolled in the Integrated Undergraduate Graduate Program (IUG), allowing me to concurrently work on my Bachelor's and Master's degree. I am also in the Schreyer's Honors College at Penn State. I am currently a Teaching Assistant for CMPEN 411:VLSI.

Related Course Work

Note that the course numbers and abbreviations have changed since I have taken them.

CSE 431&530:Computer Architecture	CSE 477&578: VLSI	CSE 471:Logical Design	CSE 472:Embedded Systems
CSE 465:Data Structures and Algorithms	CSE 428:Programming Language Concepts	CSE 411&511:Operating Systems	CSE 543:Computer Security
CSE 458/514:Networks	CSE 418:Computer Graphics	CSE 481: Artificial Intelligence
EE 310:Electronic Circuit Design	EE 317:Signals and Systems

I'm a member of the Microsystems Design Laboratory (MDL) in the CSE dept of PSU . I am working under Dr. Yuan Xie , doing research on 3D Integrated Chips (3DIC). My thesis is developing a 3DIC Flow using OpenAccess. Previously, I helped develop Scan Chain Ordering for 3DICs.

Thesis Topic: 3D IC Design Flow Using OpenAccess

A major obstacle in the development of 3D ICs is the lack of Electronic Design Automation (EDA) tools and design flows to effectively design and produce 3D ICs. In addition, because a design flow may consist of several different tools from different vendors, a lot of engineering time is spent integrating the tools into one cohesive flow. Openaccess is an effort to provide true interoperability between these tools by creating a central design database and standard API to access the data.

The goal of my thesis research is to help solve these problems to aid in the maturation of 3D IC technology. I am adapting existing 2D EDA tools to handle and design 3D ICs using an OpenAccess 3D IC model. This will create a 3D design flow with the ability to easily integrate with new and existing OA tools using the OA 3D IC model as the technology and tools mature.

3D IC

Today, most ICs have one 2D plane of active transistors. A 3D IC consists of multiple device layers stacked together with direct vertical interconnects, called through-silicon vias (TSVs) tunneling through them. Due to the stacking of multiple layers, 3D ICs offer higher packing density and a smaller footprint than traditional two-dimensional designs.

3D ICs are seen as a potential solution to the problem of increasing interconnect delays. Global interconnects do not scale as transistor technologies continue to shrink. Instead, the relative distance increases and the distance a signal can travel on these interconnects become a bottleneck, especially with increasing clock frequencies. Buffers need to be inserted to drive the signal, which also increases power consumption. In 3D ICs, the distance of the interconnects dramatically decreases because of the vertical stacking. Logic blocks that were once across the entire 2D chip, are now only separated by the vertical distance and a smaller chip size. This increases the performance, as the signal travels less distance. In addition, the power consumption decreases as it takes less power to drive the signal, and the number of buffers need is decreased.

3D ICs can also help bridge the memory wall. The speed of the CPU keeps increases faster than the speed of accessing memory. Thus, memory latency has become a major bottleneck in computer performance. An important reason for this is the limited bandwidth between memory and the CPU. 3D ICs can potentially solve this problem by stacking memory and the CPU on different tiers, and using many TSVs to connect them. This will allow more data from the memory to be transferred to the CPU in a shorter time, increasing the bandwidth and reducing memory latency.

More information regarding 3D IC research:
3D-IC.org , Dr. Xie's 3D IC research page

OpenAccess

Current design flows use a large number of design tools. Because of differences in the semantics and databases between tools, the flow may involve incompatable file formats and syntaxes. Thus, engineers need to spend a large amount of time integrating the tools, leading to fragile and error-prone flows. To mitigate this problem, OpenAccess (http://openeda.si2.org) was formed as a community effort to provide interoperability, not just data exchange, among IC design tools. OA implements an open standard application programming interface (API) and reference database.

EDA tools access design data through the OA API. By providing a standard interface to all tools, OA offers the following advantages: reduced translation steps between tools; avoiding conflicts in data representation and misinterpretation; centralize accessibility of all design data; and realizing “plug’n’play” of tools from different vendors.

3D IC Design Flows

The lack of 3D design flows and EDA tools hinders the exploration of the 3D design space and impedes the successful adoption of 3D architectures. Thus, it is imperative to develop EDA tools to construct 3D design flows, explore the 3D design space and facilitate the development of 3D technologies.

There are two problems with current 3D EDA tool efforts.
      -It is unrealistic to develop EDA tools for 3D from scratch. Ideally, design companies want to modify their existing 2D commercial design flow. There should be minimal changes on tool interfacing and methodologies in order to easily integrate the new 3D tools
      -Different companies use different design tool flows. Therefore, one 3D design methodology modified for one design may not be compatible with other flows.
New 3D tools need to address the challenge of integrating into existing 2D flows and with other 3D design flows.

I am currently developing a 3D OA model for 3D ICs and utilizing 2D EDA tools to construct a 3D IC OA design flow.This flow addresses the two problems with 3D EDA tools. The adaptation of 2D EDA tools and the use of an OpenAccess design database encourage the interfacing and growth of other tools and flows to be incorporated into the design. By creating a method to design 3D ICs with OpenAccess, this flow will aid in the exploration and analysis of the 3D IC design space, contributing to the maturation of 3D IC technology into viable product.

3DIC Scan Chains

In VLSI circuit design, scan chains are introduced to improve the testability of integrated circuits . After logic synthesis, all flip-flops in the circuits are replaced with scan flip flops. These scan flip-flops are connected sequentially to form a scan chain or multiple scan chains. Each scan flip-flop in the scan chain has two input sources: the output of the previous flip-flop in the scan chain and the output of combinational circuit. In normal mode, the scan flip-flop receives its input from the combinationorial circuit, and the circuit behaves as original designed. In test mode, a specific test vector can be scanned through the scan chain to test the behavior of the circuit given that test vector.

In scan chain design, the order of the scan chain may be important to reduce wirelength,to reduce routing congestion, for performance and power. There had been no previous work on 3D IC scan chain design. We developed three different methodologies for 3D IC scan chain construction. In approach 1, VIA3D, each layer’s scan chain nodes are ordered indepenedently, and then each chain is connected together with a TSV between each layer. In approach 2, MAP3D, all scan chains in the design are mapped to a 2D design, and then ordered. This ordering is used in the 3D IC. In approach 3, OPT3D, the 3D distance between scan chain nodes is considered to try to find a minimal wirelenght of the scan chain.

In VIA3D and MAP3D, no change is needed to the 2D ordering algorithm. However, OPT3D achieves the smaller wirelenght of the scan chain. VIA3D uses the least TSVs (only 1 between each layer), while MAP3D results in a larger number of TSVs, which may increase the wirelenght.

Publications and Presentations

[ICCD] Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. Scan Chain Design for Three-dimensional ICs. International Conference on Computer Design, 2007.
-Presented at ICCD 2007 at Squaw Valley

[EITC] Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. "Design Automation Challenges for Three-dimensional ICs", The seventh annual Emerging Information Technology Conference, 2007.

PSU Schreyer’s Honors College Scholar
IEEE Student Member
ACM Student Member
Tau Beta Pi Member,
      Corresponding Secretary PAB (Fall 07 and Spring 08)
HKN member
Lockheed Martin Engineering Scholars Award
National Scholars Honor Society
National Society of Collegiate Scholars
Golden Key Honor Society

Computer Architecture, Embedded Systems, VLSI, EDA, Security, Networks