Danfeng Zhang is an Assistant Professor at Penn State University. He received his B.S. and M.S. in Computer Science from Peking University, and his Ph.D. in Computer Science from Cornell University.

His research focuses on computer security and programming languages. His recent work is on sound and practical methods for full-system mitigation of timing channels and a general approach of diagnosing errors detected by static program analyses, such as information-flow analyses and ML type inference.

Research opportunities are available for Penn State undergraduates. Please send me an email if you're interested.

Projects

Selected Recent Publications

[Google scholar] [Complete List]
[TOPLAS]

SHErrLoc: a Static Holistic Error Locator.

with Andrew C. Myers, Dimitrios Vytiniotis and Simon Peyton‑Jones.
[USENIX Security'17]

CacheD: Identifying Cache-Based Timing Channels in Production Software.

with Shuai Wang, Pei Wang, Xiao Liu, Dinghao Wu.
[CSF'17]

Towards a Flow- and Path-Sensitive Information Flow Analysis.

with Peixuan Li.
[ASPLOS'17]

Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis.

with Andrew Ferraiuolo, Rui Xu, Andrew C. Myers and G. Edward Suh.
[POPL'17]

LightDP: Towards Automating Differential Privacy Proofs.

with Daniel Kifer.
[HPCA'16]

Lattice Priority Scheduling: Low-Overhead Timing Channel Protection for a Shared Memory Controller.

with Andrew Ferraiuolo, Yao Wang, Andrew C. Myers and G. Edward Suh.
[PLDI'15 Distinguished paper award]

Diagnosing Type Errors with Class.

with Andrew C. Myers, Dimitrios Vytiniotis and Simon Peyton‑Jones.
[ASPLOS'15]

A Hardware Design Language for Timing-Sensitive Information-Flow Security.

with Yao Wang, G. Edward Suh and Andrew C. Myers.

Teaching

Students

Grants