QUARTERLY TECHNICAL REPORT  4
FOR
Pittsburgh Digital Greenhouse
 

Electronic Design Technology Development Program
Project Solicitation 00-2
 

Project Title:   HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER
CIRCUIT FOR RADIO FREQUENCY SIGNAL
 

Principal Investigator:  Kyusun Choi
The Pennsylvania State University
Department of Computer Science and Engineering
220 Pond Laboratory
University Park, PA 16802
Phone: (814)863-1856
Fax: (814)865-3176
Email: kyusun@cse.psu.edu

Report Period:  10/9/2001 to 12/31/2001






Report 1 Webpage(.html):  http://www.cse.psu.edu/~chip/pdg/rp1/report1.html
Report 1 Slides(.ppt):   http://www.cse.psu.edu/~chip/pdg/rp1/report1.ppt

Report 2 Webpage(.html): http://www.cse.psu.edu/~chip/pdg/rp2/report2.html
Report 2 Slides(.ppt):   http://www.cse.psu.edu/~chip/pdg/rp2/report2.ppt

Report 3 Webpage(.html): http://www.cse.psu.edu/~chip/pdg/rp3/report3.html
Report 3 Slides(.ppt):   http://www.cse.psu.edu/~chip/pdg/rp3/report3.ppt

Report 4 Slides(.ppt):   http://www.cse.psu.edu/~chip/pdg/rp4/report4.ppt


TABLE OF CONTENTS

1.  Project Goals for This Quarter


2.  Accomplished Project Milestones
3.  2nd Prototype Chip Summary
4.  Chip Layout
5.  Chip Block Diagram
6.  Chip Layout Dimension
7.  Simulation Results
8.  Publication
Appendix




 

1.   Project Goals for This Quarter

        Fabricate 2nd prototype chip in 0.18um CMOS, containg 6 and 8 bit TIQ ADC  circuits
        Test 2nd prototype chip
        Final evaluation of 1st and 2nd prototype chips
        Final report and presentation

2.   Accomplished Project Milestones

        Received and tested 2nd prototype chip in 0.18um CMOS
        The chip test summary:
        (The chip contains total 10 ADCs )

                1.     6bit ADC with L = 0.18um and ROM Decoder, working with reduced precision
                2.     6bit ADC with L = 0.50um and  ROM Decoder, working with reduced precision
                3.     6bit ADC with L = 1.00um and  ROM Decoder, working with full 6 bit precision
                4.     6bit ADC with L = 1.00um and  Fat Tree Decoder, working with full 6 bit precision
                5.     6bit ADC with L = 1.00um and  Pipeline,
                6.     6bit ADC with L = 1.00um and  Sample & Hold,
                7.     8bit ADC with L = 0.50um and  ROM Decoder, working with reduced precision
                8.     8bit ADC with L = 1.00um and  ROM Decoder, working with reduced precision
                9.     9bit ADC with L = 1.00um and  ROM Decoder, working with reduced precision
                10.  9bit ADC with L = 1.50um and  ROM Decoder, working with reduced precision
 

3.   2nd Prototype Chip Summary

                - Die size: 2.64 * 2.64 mm2 (total)
                                     1.88 * 1.88 mm2 (core)

                - 0.18 um Digital Logic CMOS

                - 56,069 Transistors

                -  84 pins,  (18 pins for power)
 

 2nd prototype chip GDS file (116MByte, please use "Save as" to download the file)
4.   Chip Layout Dimension
 
ADCs
Size(W*H) um
Area(mm2)
Layout
6bit 0.18um with ROM
188.840 * 194.700
0.037
 Click
6bit 0.50um with ROM
188.980 * 239.500
0.045
 Click
6bit 1.00um with ROM
255.020 * 290.700
0.074
 Click
6bit 1.00um with Fat Tree
251.850 * 272.300
0.069
 Click
6bit 1.00um with Pipeline
 294.530 * 290.710
0.086
 Click
6bit 1.00um with Sample & Hold
 255.020 * 290.700
0.074
 Click
8bit 0.50um with ROM
202.250 * 815.550
 0.165
 Click
8bit 1.00um with ROM
266.400 * 1019.780
 0.272
 Click
9bit 1.00um with ROM
438.660 * 1225.100
 0.537
 Click
9bit 1.50um with ROM
375.630 * 1583.500
 0.595
 Click

        a.  Custom pad-frame design
        b.  Floor-plan design and place \& route 6, 8, and 9 bit ADCs (total 10 ADCs)

    - Pad
        Size(W*H): 2640 um * 2640 um
        Layout

    - Multiplexor
        Size(W*H): 48.130 um * 33.4 um
        Layout

        Chip Circuit Diagram
 

5.   Simulation Results

        Max. Speed and Power
 
ADCs
Max. Speed under TSMC_TT
Max. Speed under process variations
Analog Power
6bit 0.18um with ROM
2000 MSPS
1250 MSPS
149.18 mW
6bit 0.50um with ROM
1666 MSPS
1000 MSPS
62.03 mW
6bit 1.00um with ROM
1111 MSPS
667 MSPS
54.47 mW
6bit 1.00um with Fat Tree
1111 MSPS
714 MSPS
36.41 mW
8bit 0.50um with ROM
2000 MSPS
1000 MSPS
181.12 mW
8bit 1.00um with ROM
1666 MSPS
714 MSPS
151.13 mW
9bit 1.00um with ROM
667 MSPS
476 MSPS
269.53 mW
9bit 1.50um with ROM
500 MSPS
400 MSPS
153.89 mW

        Worst case delay

(1) Input Swing: 0.0V - 1.8V

   (a) Actual measment

   (b) Simulation with T1AX_LO_EPI

(nSec.)
ADCs
tcomp
tgb
trom
tbuffer
6bit 0.18um with ROM
0.116
0.460
1.101
1.284
6bit 0.50um with ROM
0.306
0.658
1.485
1.669
6bit 1.00um with ROM
0.696
1.063
2.711
2.894
6bit 1.00um with Fat Tree
0.696
0.995
2.158
2.187
8bit 0.50um with ROM
0.307
0.660
1.312
1.468
8bit 1.00um with ROM
0.697
1.064
2.527
2.720
9bit 1.00um with ROM
0.711
1.178
3.407
3.664
9bit 1.50um with ROM
1.270
1.755
3.847
4.045

   (c) Simulation with TSMC_TT

(nSec.)
ADCs
tcomp
tgb
trom
tbuffer
6bit 0.18um with ROM
0.084
0.358
0.893
1.030
6bit 0.50um with ROM
0.237
0.521
1.200
1.320
6bit 1.00um with ROM
0.540
0.837
2.170
2.330
6bit 1.00um with Fat Tree
0.540
0.784
1.670
1.690
8bit 0.50um with ROM
0.240
0.525
0.935
1.040
8bit 1.00um with ROM
0.538
0.836
1.940
2.070
9bit 1.00um with ROM
0.549
0.932
2.610
2.780
9bit 1.50um with ROM
0.984
1.380
2.900
3.030

(2) Input Swing: 0.5V - 1.1V

  (a) Actual measument

  (b) Simulation with T1AX_LO_EPI

(nSec.)
ADCs
tcomp
tgb
trom
tbuffer
6bit 0.18um with ROM
0.164
0.509
1.186
1.346
6bit 0.50um with ROM
0.472
0.833
1.726
1.949
6bit 1.00um with ROM
1.223
1.605
5.460
5.662
6bit 1.00um with Fat Tree
1.224
1.539
2.530
2.560
8bit 0.50um with ROM
0.474
0.835
1.542
1.686
8bit 1.00um with ROM
1.226
1.609
3.518
3.696
9bit 1.00um with ROM
1.263
1.750
4.480
4.711
9bit 1.50um with ROM
2.309
2.815
5.874
6.054

  (c) Simulation with TSMC_TT

(nSec.)
ADCs
tcomp
tgb
trom
tbuffer
6bit 0.18um with ROM
0.122
0.395
0.969
1.090
6bit 0.50um with ROM
0.338
0.623
1.470
1.580
6bit 1.00um with ROM
0.867
1.160
3.750
3.890
6bit 1.00um with Fat Tree
0.867
1.110
1.960
1.980
8bit 0.50um with ROM
0.340
0.624
1.090
1.210
8bit 1.00um with ROM
0.868
1.170
2.810
2.950
9bit 1.00um with ROM
0.896
1.280
3.540
3.720
9bit 1.50um with ROM
1.660
2.060
4.720
4.860

            INL and DNL Measurements Over Process Variation

(1)  Simulation under TSMC_TT

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.003
0.003
6bit 0.50um with ROM
0.005
0.007
6bit 1.00um with ROM
0.008
0.006
6bit 1.00um with Fat Tree
0.008
0.006
8bit 0.50um with ROM
0.090
0.076
8bit 1.00um with ROM
0.084
0.077
9bit 1.00um with ROM
 0.150
 0.104
9bit 1.50um with ROM
 0.377
 0.250

(2) Simulation under TSMC_FF

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.068
0.697
6bit 0.50um with ROM
0.079
0.327
6bit 1.00um with ROM
0.058
0.540
6bit 1.00um with Fat Tree
0.058
0.540
8bit 0.50um with ROM
 0.185
 1.316
8bit 1.00um with ROM
 0.145
 2.295

(3) Simulation under TSMC_FS

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.023
0.226
6bit 0.50um with ROM
0.082
0.271
6bit 1.00um with ROM
0.035
0.351
6bit 1.00um with Fat Tree
0.035
0.351
8bit 0.50um with ROM
 0.209
 1.119
8bit 1.00um with ROM
 0.199
 1.450

(4) Simulation under TSMC_SS

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.056
0.476
6bit 0.50um with ROM
0.128
0.536
6bit 1.00um with ROM
0.129
0.777
6bit 1.00um with Fat Tree
0.129
0.777
8bit 0.50um with ROM
 0.194
 2.170
8bit 1.00um with ROM
 0.214
 3.244

(5) Simulation under TSMC_SF

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.026
0.245
6bit 0.50um with ROM
0.051
0.288
6bit 1.00um with ROM
0.062
0.385
6bit 1.00um with Fat Tree
0.062
0.385
8bit 0.50um with ROM
 0.277
 1.264
8bit 1.00um with ROM
 0.189
 1.566

(6) Simulation under T18H

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.058
0.752
6bit 0.50um with ROM
 0.123
 1.653
6bit 1.00um with ROM
0.148
1.787
6bit 1.00um with Fat Tree
0.148
1.787
8bit 0.50um with ROM
0.293
6.784
8bit 1.00um with ROM
0.234
7.336
9bit 1.00um with ROM
 0.457
 15.279
9bit 1.50um with ROM
 0.528
 12.187

(7) Simulation under T16X

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.056
0.729
6bit 0.50um with ROM
0.115
1.689
6bit 1.00um with ROM
0.150
1.813
6bit 1.00um with Fat Tree
0.150
1.813
8bit 0.50um with ROM
0.291
6.923
8bit 1.00um with ROM
0.241
7.500
9bit 1.00um with ROM
 0.446
 15.338
9bit 1.50um with ROM
 0.520
 12.100

(8) Simulation under T15J

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.032
0.189
6bit 0.50um with ROM
0.119
1.207
6bit 1.00um with ROM
0.164
1.408
6bit 1.00um with Fat Tree
0.164
1.408
8bit 0.50um with ROM
0.259
5.083
8bit 1.00um with ROM
0.254
5.754
9bit 1.00um with ROM
 0.456
 12.101
9bit 1.50um with ROM
 0.497
 8.626

(9) Simulation under T14B

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.074
0.735
6bit 0.50um with ROM
0.110
1.192
6bit 1.00um with ROM
0.149
1.352
6bit 1.00um with Fat Tree
0.149
1.352
8bit 0.50um with ROM
0.276
4.944
8bit 1.00um with ROM
0.239
5.732
9bit 1.00um with ROM
 0.454
 12.009
9bit 1.50um with ROM
 0.513
 8.513

(10) Simulation under  T12K

(LSB)
ADCs
DNL
INL
6bit 0.18um with ROM
0.032
0.177
6bit 0.50um with ROM
0.115
1.016
6bit 1.00um with ROM
0.156
1.313
6bit 1.00um with Fat Tree
0.156
1.313
8bit 0.50um with ROM
0.259
4.349
8bit 1.00um with ROM
0.257
5.461
9bit 1.00um with ROM
 0.436
 11.501
9bit 1.50um with ROM
 0.493
 7.987

6.   Publication

(1) J. Yoo, K. Choi, and A. Tangel, A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications, the IEEE Computer Society Workshop on VLSI, April 2001.

(2) J. Yoo, D. Lee, K. Choi, and A. Tangel, Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications, the IEEE International ASIC/SOC Conference, September 2001.

(3) D. Lee, J. Yoo, and K. Choi, Design Method and Automation of Comparator Generation for Flash A/D Converter, the IEEE Internation Symposium on Quality Electronic Design, March 2002.
 



Appendix

0.  Range of Comparator Widths
1.  Gain Booster Slope(gain) result
2.  Chip pin configuration
3.  Pin function descriptions
4.  Chip circuit diagram
5.  Chip layout block diagram
6.  Package wire boding diagram
7.  Presentation slides (Power Point file)
8.  2nd prototype chip GDS file (116MByte, please use "save as" to download the file)
9.  PCB file
10.  2nd prototype chip test board description