QUARTERLY TECHNICAL REPORT  2
FOR
Pittsburgh Digital Greenhouse
 

Electronic Design Technology Development Program
Project Solicitation 00-2
 
 

Project Title:   HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER
CIRCUIT FOR RADIO FREQUENCY SIGNAL
 
 

Principal Investigator:  Kyusun Choi
The Pennsylvania State University
Department of Computer Science and Engineering
220 Pond Laboratory
University Park, PA 16802
Phone: (814)863-1856
Fax: (814)865-3176
Email: kyusun@cse.psu.edu
 

Report Period:  4/2/2001 to 7/2/2001
 
 

Report 2 Webpage(.html): http://www.cse.psu.edu/~chip/pdg/rp2/report2.html
Report 2 Slides(.ppt):        http://www.cse.psu.edu/~chip/pdg/rp2/report2.ppt

Report 1 Webpage(.html):  http://www.cse.psu.edu/~chip/pdg/rp1/report1.html
Report 1 Slides(.ppt):         http://www.cse.psu.edu/~chip/pdg/rp1/report1.ppt





 

TABLE OF CONTENTS


1.  Summary of the Quarterly Technical Report 2

2.  Prototype Chip

3.  Chip Test Results
        1.  ADC operation (oscilloscope picture)
        2.  Delay of Pad and Multiplexor
        3.  ADC signal propagation
        4.  INL and DNL measurements
        5.  ADC power consumption
        6.  Process variation effects
        7.  Precision measurement
        8.  Noise

4.  Test Evaluation
       1.  All 25 prototype chips are working
       2.  Signal delay
       3.  Reduced precision
       4.  Power consumption
       5.  INL and DNL
       6.  Process parameter variation on same wafer
       7.  Further testing to be done

5.  Second Prototype Chip Design
       1.  0.18um CMOS technology
       2.  New pad frame design
       3.  Limit LSB's Delta-W, dW = 0.1um or 0.05um
       4.  Sample and hold plus 2 stage pipeline
       5.  Single inverter comparator instead of double inverter comparator
       6.  ADC input shielding, on chip and off chip

6.  Conclusion

Appendix



 

1.  Summary of the Quarterly Technical Report 2


PROJECT GOALS FOR THIS QUARTER

(1) First prototype chip test
(2) Test report
(3) Design second prototype chip: 6 and 8 bit flash ADC in 0.18um technology

ACCOMPLISHED PROJECT MILESTONES FOR THIS QUARTER

(1) Received first prototype chips containing the 6, 8, and 9 bit TIQ based flash ADC circuits,
       fabricated with 0.25 um CMOS technology
        a.  Total 25 identical prototype chips are received
        b.  Total six ADCs are in each prototype chip:
                i.     a 6bit high speed ADC
                ii.    a 6bit low power ADC
                iii.   an 8bit high speed ADC
                iv.   an 8bit low power ADC
                v.    a 9bit high speed ADC
                vi.   a 9bit low power ADC

(2) Initial test results show that all 25 prototype chips are working

(3) Initial test results for six ADCs on each prototype chip

                i.     a 6bit high speed ADC:     4bit precision, 3.799ns ADC signal delay
                ii.    a 6bit low power ADC:     6bit precision, 21.404ns ADC signal delay
                iii.   an 8bit high speed ADC:   5bit precision, 7.249ns ADC signal delay
                iv.   an 8bit low power ADC:   7bit precision, 18.612ns ADC signal delay
                v.    a 9bit high speed ADC:     6bit precision, 27.762ns ADC signal delay
                vi.   a 9bit low power ADC:     8bit precision, 83.595ns ADC signal delay

(4) Chip testing and parameter extraction

(5) Second prototype chip design in 0.18um technology (on going)
       a.  Tape-out target date: 8/5/2001
        b.  Vendor: MOSIS with TSMC 0.18 um foundry
        c.  Expected prototype chip delivery date: 10/25/2001
 

FACULTY AND STUDENTS SUPPORTED

(1) Principal Investigator: Kyusun Choi, Assistant Professor, Department of Computer Science and Engineering
(2) Graduate Assistant 1: Jincheol Yoo, Ph.D. student, Department of Computer Science and Engineering
(3) Graduate Assistant 2: Daegyu Lee, MS student, Department of Computer Science and Engineering
 

PUBLICATION

Paper Published :  J. Yoo, K. Choi, and A. Tangel,  A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications, the IEEE Computer Society Workshop on VLSI, April 2001, pp. 135-139.

Paper Accepted:  J. Yoo, D. Lee, K. Choi, and A. Tangel, Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications, the IEEE International ASIC/SOC Conference, September 2001, pp. 455-459.
 


2.  Prototype Chip

  1. Received first prototype chips

  2. Total 25 identical prototype chips are received.  Chips are fabricated with 0.25um digital CMOS technology.
    (a)  Prototype chip photo
    (b)  Chip die photo (5 layers of metal covers most of the active area)
    (c)  Chip die corner photo
    (d)  Output pad driver photo  (only visible active area)
    (e)  Prototype chip tester setup
     
  3. Total six ADCs are in each prototype chip:
    1. a 6bit high speed ADC
    2. a 6bit low power ADC
    3. an 8bit high speed ADC
    4. an 8bit low power ADC
    5. a 9bit high speed ADC
    6. a 9bit high speed ADC

    7.  


3.  Chip Test Results

        1.  ADC operation (oscilloscope picture)
              (1)  100Khz triangle wave input to 6bit low power ADC

              (2)  400Khz Sine wave input to 6bit low power ADC

              (3)  1Mhz Square wave input to 6bit low power ADC

        2.  Delay of Pad and Multiplexor
              (1)  Pad and multiplexor circuit
 
 

              (2)  Actual measurement (Tin to Tout)


(nSec.)
 ADCs
Rising delay
Falling delay
Average delay
chip #3
3.450
2.850
3.150
chip #6
3.475
2.825
3.150
chip #7
4.250
2.875
3.563

              (2)  Simulation with T14Y_LO_EPI
                     - mux delay: 0.414 nSec.
                     - Pad + Mux delay: 1.144 nSec.

              (3)  Simulation with TSMC_TT
                     - mux delay: 0.332 nSec.
                     - Pad + Mux delay: 0.864 nSec.

        3.  ADC signal propagation

                (1)  input swing 0.0V to 2.5V
                     (a)  Actual measurement

(nSec.)
 
6bit high speed
6bit low power
8bit high speed
8bit low power
9bit high speed
9bit low power
chip #6
3.924
21.662
6.887
18.687
27.612
84.162
chip #15
3.924
21.562
7.787
18.662
27.712
82.062
chip #16
3.549
20.987
7.074
18.487
27.962
84.562

                     (b)  Simulation with T14Y_LO_EPI ( t_p = (tpLH + tpHL)/2 )

(nSec.)
ADCs
t_comp
t_gb1
t_gb2
t_gen
t_rom
t_out
6bit high speed
0.352
0.595
 
0.724
1.854
2.216
6bit low power
2.183
2.596
 
2.784
4.857
5.250
8bit high speed
0.358
0.556
0.800
1.066
1.624
1.914
8bit low power
0.873
1.103
1.341
1.534
2.169
2.502
9bit high speed
0.696
0.938
1.216
1.566
2.687
3.075
9bit low power
2.264
2.569
2.846
3.198
4.193
4.544

                     (c)  Simulation with TSMC_TT ( t_p = (tpLH + tpHL)/2 )

(nSec.)
ADCs
t_comp
t_gb1
t_gb2
t_gen
t_rom
t_out
6bit high speed
0.287
0.488
 
0.587
1.570
1.850
6bit low power
1.972
2.322
 
2.482
4.205
4.506
8bit high speed
0.292
0.449
0.656
0.863
1.225
1.430
8bit low power
0.705
0.903
1.089
1.264
1.701
1.931
9bit high speed
0.579
0.781
1.014
1.287
2.055
2.330
9bit low power
2.066
2.319
2.551
2.823
3.491
3.740

               (2)  input swing 0.6V to 1.7V
                     (a)  Actual measurement

(nSec.)
 
6bit high speed
6bit low power
8bit high speed
8bit low power
9bit high speed
9bit low power
chip #6
6.912
38.911
14.562
17.962
31.862
108.862
chip #15
5.562
37.861
7.487
17.574
31.211
106.862
chip #16
3.512
38.861
7.687
17.462
34.212
109.762

                     (b)  Simulation with T14Y_LO_EPI ( t_p = (tpLH + tpHL)/2 )

(nSec.)
ADCs
range(volt)
t_comp
t_gb1
t_gb2
t_gen
t_rom
t_out
6bit high speed
0.65 - 1.75
0.614
0.876
 
1.060
2.017
2.383
6bit low power
0.50 - 1.76
3.179
3.682
 
3.872
7.808
8.186
8bit high speed
0.65 - 1.75
0.434
0.631
0.915
1.141
1.721
2.012
8bit low power
0.58 - 1.72
1.089
1.320
1.604
1.886
2.558
2.914
9bit high speed
0.58 - 1.72
1.089
1.320
1.573
1.917
3.060
3.483
9bit low power
0.50 - 1.76
3.446
3.793
4.067
4.415
5.404
5.775

                     (c)  Simulation with TSMC_TT ( t_p = (tpLH + tpHL)/2 )

(nSec.)
ADCs
range(volt)
t_comp
t_gb1
t_gb2
t_gen
t_rom
t_out
6bit high speed
0.65 - 1.75
0.540
0.755
 
0.899
1.734
2.011
6bit low power
0.50 - 1.76
2.500
2.909
 
3.064
6.202
6.481
8bit high speed
0.65 - 1.75
0.381
0.542
0.779
0.933
1.333
1.520
8bit low power
0.58 - 1.72
0.819
1.000
1.237
1.481
1.955
2.244
9bit high speed
0.58 - 1.72
0.819
1.000
1.237
1.505
2.302
2.629
9bit low power
0.50 - 1.76
2.701
3.001
3.236
3.509
4.183
4.437

        4.  INL and DNL measurements
              (1)  Actual measurement


DNL and INL of 6bit Low Power ADC in chip #12

(LSB)
ADCs
DNL
INL
chip#6   6bit Low Power
0.49
1.19
chip#12 6bit Low Power
0.27
1.20

              (2)  Simulation with TSMC_TT

(LSB)
ADCs
DNL
INL
6bit Low Power
0.02
0.01
6bit High Speed
0.01
0.01
8bit Low Power
0.17
0.10
8bit High Speed
0.04
0.03
9bit Low Power
0.21
0.22
9bit High Speed
0.26
0.23

              (3)  Simulation with T14Y_LO_EPI

(LSB)
ADCs
DNL
INL
6bit Low Power
0.08
0.34
6bit High Speed
0.07
0.48
8bit Low Power
0.18
1.21
8bit High Speed
0.09
1.96
9bit Low Power
0.29
2.78
9bit High Speed
0.22
2.43

              (4)  Actual measurement, power supply variation
              (5)  Actual measurement, temperature variation

        5.  ADC power consumption
              (1)  Actual measurement

(mWatt)

 
ADCs
Sampling rate (MSPS)
Avg. Power
Max. Power
6bit high speed
continuous
109.38
N/A
6bit low power
continuous
35.25
N/A
8bit high speed
continuous
170.5
N/A
8bit low power
continuous
121.25
N/A
9bit high speed
continuous
200.375
N/A
9bit low power
continuous
179.625
N/A

              (2)  Simulation with T14Y_LO_EPI

(mWatt)
ADCs
 Sampling rate (MSPS)
Avg. Power
Max. Power
6bit high speed
1000 
65.06
94.73
6bit low power
400 
39.81
70.75
8bit high speed
667
238.43
330.80
8bit low power
500
171.81
255.78
9bit high speed
250
331.16
470.48
9bit low power
200
281.59
429.74

              (3)  Simulation with TSMC_TT

(mWatt)
ADCs
 Sampling rate (MSPS)
Avg. Power
Max. Power
6bit high speed
1000 
68.96
101.86
6bit low power
400 
37.57
70.03
8bit high speed
667
254.76
353.78
8bit low power
500
165.29
254.87
9bit high speed
250
317.40
469.46
9bit low power
200
260.11
417.15

        6.  Process variation effects
              (1)  Vastart and Vaend for 25 chips

(Volt.)
 
6bit high speed
 
6bit low power
 
8bit high speed
 
8bit low power
 
9bit high speed
 
9bit low power
 
chip No.
Vastart
Vaend
Vastart
Vaend
Vastart
Vaend
Vastart
Vaend
Vastart
Vaend
Vastart
Vaend
1
0.793
1.627
0.576
1.669
0.793
1.617
0.663
1.610
0.671
1.604
0.572
1.670
2
0.780
1.624
0.572
1.670
0.789
1.615
0.662
1.610
0.665
1.601
0.575
1.674
3
0.785
1.617
0.575
1.664
0.786
1.615
0.660
1.609
0.668
1.594
0.575
1.666
4
0.762
1.644
0.567
1.683
0.769
1.649
0.652
1.619
0.656
1.615
0.566
1.685
5
0.784
1.638
0.574
1.668
0.787
1.633
0.663
1.609
0.666
1.601
0.574
1.671
6
0.777
1.626
0.573
1.666
0.784
1.622
0.664
1.608
0.667
1.598
0.574
1.666
7
0.779
1.624
0.572
1.667
0.783
1.623
0.659
1.613
0.664
1.603
0.569
1.674
8
0.776
1.627
0.564
1.666
0.761
1.621
0.652
1.607
0.654
1.596
0.563
1.669
9
0.760
1.627
0.563
1.667
0.777
1.617
0.649
1.608
0.652
1.599
0.561
1.672
10
0.778
1.639
0.571
1.666
0.775
1.639
0.662
1.611
0.668
1.601
0.572
1.670
11
0.779
1.626
0.573
1.670
0.780
1.621
0.661
1.608
0.667
1.599
0.574
1.670
12
0.778
1.634
0.568
1.669
0.777
1.624
0.654
1.608
0.659
1.601
0.568
1.670
13
0.769
1.629
0.570
1.669
0.779
1.621
0.659
1.608
0.663
1.596
0.569
1.672
14
0.786
1.620
0.573
1.666
0.785
1.637
0.664
1.607
0.666
1.596
0.573
1.669
15
0.775
1.622
0.571
1.661
0.786
1.635
0.657
1.602
0.665
1.599
0.571
1.668
16
0.775
1.620
0.567
1.667
0.795
1.632
0.650
1.607
0.660
1.599
0.566
1.670
17
0.782
1.630
0.571
1.669
0.778
1.644
0.662
1.611
0.669
1.601
0.575
1.672
18
0.771
1.635
0.566
1.670
0.775
1.633
0.655
1.608
0.662
1.602
0.565
1.672
19
0.780
1.628
0.575
1.668
0.791
1.621
0.664
1.607
0.671
1.600
0.575
1.670
20
0.779
1.629
0.575
1.666
0.783
1.621
0.659
1.609
0.667
1.600
0.575
1.671
21
0.774
1.624
0.570
1.666
0.786
1.640
0.659
1.611
0.667
1.601
0.572
1.671
22
0.775
1.631
0.573
1.670
0.786
1.636
0.662
1.613
0.671
1.607
0.573
1.673
23
0.757
1.642
0.560
1.674
0.760
1.638
0.647
1.615
0.650
1.605
0.558
1.674
24
0.774
1.649
0.576
1.695
0.775
1.660
0.660
1.630
0.668
1.626
0.575
1.694
25
0.786
1.621
0.577
1.666
0.787
1.638
0.664
1.605
0.672
1.599
0.577
1.670

              (2)  Spice file, T14Y_LO_EPI, click here

        7.  Precision measurement
             (1)  Effective number of bits observed
                      (a)  a 6bit high speed ADC:     4bit precision
                      (b)  a 6bit low power ADC:     6bit precision
                      (c)  an 8bit high speed ADC:   5bit precision
                      (d)  an 8bit low power ADC:   7bit precision
                      (e)  a 9bit high speed ADC:     6bit precision
                      (f)   a 9bit low power ADC:     8bit precision

              (2)  LSB's Delta-W (from layout design)
 
ADCs
dLSB (mV)
dWhp (um)
dWhn (um)
dWmp (um)
dWmn (um)
dWlp (um)
dWln (um)
6bit high speed
14.52
0.190
0.094
0.330
0.172
0.244
0.118
6bit low power
17.16
0.376
0.192
1.714
0.866
0.730
0.366
8bit high speed
3.54
0.076
0.022
0.072
0.046
0.056
0.020
8bit low power
3.76
0.076
0.028
0.198
0.094
0.092
0.050
9bit high speed
1.86
0.106
0.014
0.094
0.048
0.044
0.054
9bit low power
2.09
0.028
0.020
0.214
0.104
0.062
0.042

        8.  Noise
              (1)  Power supply noise

              (2)  Noise on ADC input pin

              (3)  Effects of noise (1) and (2) on the ADC output

4.  Test Evaluation


       1.  All 25 prototype chips are working
                 (1)  Best working ADC is the 6bit low power ADC:
                              *  Full 6bit precision without missing code
                 (2)  Better working ADC is the 9bit low power ADC:
                              *  7bit operation without missing code
                              *  8bit operation with few missing code
                 (3)  Other ADCs:
                              *  Working but with lower precision
                              *  High speed ADC outputs show more noise and less precision

       2.  Signal delay
                 (1)  The original ADC design and simulation was based on the TSMC_TT parameters
                 (2)  The wafer test result produced T14Y_LO_EPI parameters
                             Re-simulation with T14Y_LO_EPI parameters show 10% - 30% more signal delays
                 (3)  The actual measurements on a prototype chip show at least 50% longer signal delays
                             Possible reasons are:
                                     (a)  Significant under estimation of the load condition, load caps and RF effects
                                     (b)  Layout to circuit extraction tool being not accurate
                                     (c)  Bandwidth of the signal source and measuring tools limited
                                     (d)  Bread boarding and power supply limits

       3.  Reduced precision
                 (1)  First reason for the reduced precision is the process limitation
                              *  Although layout dimension can be specified in 0.01um steps, mask making and
                                         physical dimension control in 0.01um step is not possible, considering the
                                         minimum feature size of 0.24um
                              *  LSB's Delta-W tabulation shows that the high speed ADCs have smaller Delta-W
                              *  High speed ADCs suffer more loss of precision
                 (2)  Another reason for the reduced precision is due to the on-chip power distribution
                              *  Pad frame design does not separate analog power line from digital power line
                              *  Digital circuit generate excessive noise on the power supply line causing the
                                          sensitive analog comparators to oscillate
                 (3)  Another reason for the reduced precision is due to the noise on ADC input
                              *  High freq. noise appear on the ADC input
                              *  High freq. noise from power supply line (mainly due to digital switching and
                                          pad drivers) coupled to ADC input.   Again it cause the analog comparators to
                                          oscillate before settled on steady state

       4.  Power consumption
                 (1)  Actual measured power for each ADC shows good match with simulation results
                 (2)  Overall 10% - 20% less power consumption measured than the simulation results

       5.  INL and DNL
                 (1)  INL and DNL are significantly increased on the actual measured result compared to
                              the simulation results
                 (2)  INL increase is more than 1.0 bit LSB
                 (3)  DNL increase is less than 0.4 bit LSB

       6.  Process parameter variation on same wafer
                 (1)  Less than 3% variation of Vastart among 25 chips
                 (2)  Overall consistent among the chip

       7.  Further testing to be done
                 (1)  DC specification test
                              *  Temperature drift effect
                              *  Power supply variation
                 (2)  AC specification test and characterization
                              *  Signal-to-noise and distortion ratio
                              *  Effective number of bits
                              *  Signal-to-noise ratio
                              *  Total harmonic distortion
                              *  Spurious free dynamic range
                              *  Other dynamic performance
 

5.  Second Prototype Chip Design

       1.  0.18um CMOS technology
                 (1)  Next chip design targeted for the 0.18um CMOS technology
                              *  6bit, 8bit, and 9bit ADCs will be designed
                              *  Expecting better precision due to finer control of structure dimension
                              *  Expecting slightly more power consumption
                              *  Expecting slightly faster operation
                              *  Plan to put more ADCs and test structure on a chip
                 (2)  Use 84pin package
                              *  For more power pins, analog and digital separated
                              *  For more output pins, testing and internal observation

       2.  New pad frame design
                 (1)  3 sets of separate on-chip power supply distribution system
                              *  Analog power rail for the comparators and gain booster
                              *  Digital power rail for 01 generator, ROM, and ROM output buffer, and Mux
                              *  Pad driver power rail, large power swing
                 (2)  84 pin
                              *  32 power supply pins
                              *  10 analog input pins
                              *  26 ADC output pins
                              *  etc.

       3.  Limit LSB's Delta-W, dW = 0.1um or 0.05um
                 (1)  To guarantee comparator operation for LSB
                 (2)  Add dW test structure to identify dW limit on 0.18um technology

       4.  Sample and hold plus 2 stage pipeline
                 (1)  Add sample and hold circuit to ADCs
                 (2)  Add digital pipeline registers at the end of the gain booster, at the end of ROM
                 (3)  Expecting at least doubling of the ADC speed

       5.  Single inverter comparator instead of double inverter comparator
                 (1)  Add test ADC with single inverter comparator design
                 (2)  Determine high frequency operation limits

       6.  ADC input shielding, on chip and off chip
                 (1)  Provide analog input shielding on-chip
                 (2)  Use highly shielded signal input leads during testing
                 (3)  Provide printed circuit board design for testing of ADCs, instead of bread boarding
 

6.  Conclusion

       1.  Mission success for the first prototype chip fabrication
                 (1)  Verification of 6bit TIQ based ADC idea, it works
                 (2)  Verification of 8bit TIQ based ADC idea, it almost works
                             *  7bit works without missing code
                             *  8bit can be made to work without difficulty
                 (3)  Identified the limits of TIQ bases ADC idea,
                              limits of fine control of on-chip structure dimension, namely LSB's Delta-W
                 (4)  Power estimation verified, good match

       2.  Major mistakes on the first prototype chip design
                 (1)  Not separating the analog power supply from the digital power supply on chip
                 (2)  Lack of on-chip analog input shielding
                 (3)  Significant under estimation of on-chip parasitics,  major improvement of the
                              layout to circuit extraction tool needed for better estimation of speed

       3.  Expectation of second prototype chip
                 (1)  Full precision 6bit and 8bit ADCs on-chip
                 (2)  Chip operating speed above 200MSPS, push toward 1GSPS
                 (3)  Maximum ADC operating power less than 200mW
 

Appendix

1.  Chip pin configuration diagram
2.  Pin function descriptions
3.  Chip circuit diagram
4.  Chip layout block diagram
5.  Package wire boding diagram
6.  Presentation slides (Power Point file)