CHIP CIRCUIT DIAGRAM

PADs



 
 


 
 


Pad delay test circuit



6bit ADCs

6bit Additional ADCs

8bit ADCs


9bit ADCs


ADC Circuit Schematic Diagram

The second prototype chip contains the following 10 ADCs:
  1. 6bit 0.18um with ROM ADC
  2. 6bit 0.50um with ROM ADC
  3. 6bit 1.00um with ROM ADC
  4. 6bit 1.00um with Fat Tree ADC
  5. 6bit 1.00um with Pipeline ADC
  6. 6bit 1.00um with Sample & Hold ADC
  7. 8bit 0.50um with ROM ADC
  8. 8bit 1.00um with ROM ADC
  9. 9bit 1.00um with ROM ADC
  10. 9bit l.50um with ROM ADC
The basic circuit schematic diagram for the above 10 TIQ Flash ADCs are same as that of the 3bit TIQ Flash ADC circuit schematic diagram shown below in Figure 1. The specific circuit schematic diagram differences for each of the 10 TIQ Flash ADCs are specified in Table 1 below.


Figure 1. A 3bit TIQ Flash ADC Circuit
 
 
 
 
 

Table 1.   The specific circuit schematic diagrams differences from the 3bit TIQ Flash ADC circuit.

 
Number of comparators
Gain booster
ROM size
Fig 1,  3bit ADC circuit
7
4 inverters
7 X 3
6bit 0.18um w/ ROM ADC
63
6 inverters
63 X 6
6bit 0.50um w/ ROM ADC
63
6 inverters
63 X 6
6bit 1.00um w/ ROM ADC
63
 6 inverters
63 X 6
6bit 1.00um w/ Fat Tree ADC
63
 6 inverters
63 X 6
6bit 1.00um w/ Pipeline ADC
63
 6 inverters
63 X 6
6bit 1.00um w/ S&H ADC
63
 6 inverters
63 X 6
8bit 0.50um w/ ROM ADC
255
6 inverters
255 X 8
8bit 1.00um w/ ROM ADC
255
6 inverters
255 X 8
9bit 1.00um w/ ROM ADC
511
8 inverters
511 X 9
9bit 1.50um w/ ROM ADC
511
8 inverters
511 X 9

The layout design of the TIQ Flash ADC follows closely with the shown circuit diagram.  A row layout is designed, and the rows are stacked.    A row consists of a comparator, a gain booster, a 0-1 generator, and a ROM (one row).
In the second prototype chip, each of the ADC layouts are added with two dummy rows, one at the top of the stack and one at the bottom of the stack.