Publications

• B. Vaidyanathan, W. -L. Hung, F. Wang, Y. Xie, V. Narayanan, M. J. Irwin, "Architecting Microprocessor Components in 3D Design Space", In the proceedings of 20th International Conference on VLSI Design 2007.[pdf] [ppt]
  [This work was supported in part by NSF Career Award #0093085, NSF grant #0202007, and by a grant from MARCO/GSRC]
• F. Wang, Y. Xie, R. Rajaraman, B. Vaidyanathan, "Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model", In the proceedings of 20th International Conference on VLSI Design 2007.[pdf] [ppt]
• B. Vaidyanathan, Y. Xie, V. Narayanan, R. Luo, "Leakage Optimized DECAP Design for FPGAs", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2006. [pdf] [ppt]
  [This work was supported in part by NSF grant #0454123 and by a grant from GSRC]
• B. Vaidyanathan, Y. Xie, "Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression", IEEE International SOC Conference, Austin, TX, Aug. 2006. [pdf] [ppt]
• B. Vaidyanathan, Y. Xie, V. Narayanan, H. Zheng, "Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits", The Second Workshop on System Effects of Logic Soft Errors (SELSE), 2006. [pdf] [ppt]
  [This work was supported in part by NSF grant #0454123]