When powered on, the SA-1110 initially runs at its lowest frequency. Software has to set the CPU to speed by changing core clock configuration field(CCF<4:0>) in the power manager phase-locked loop (PLL) configuration register (PPCR). For more detail, please see Table 8-1 in SA-1110 Developer's Manual section 8.2. Software can set the CCF<4:0> to a lower speed to power down the CPU during operation. Note that there will be a 150 microseconds period during which the CPU can not respond to external events and that the OS timer is stopped during this period. The programmer must take these side effects into account when software uses this technique to power down. For more details, please see SA-1110 Developer's Manual section 8.2.1.
When switching CPU clock rates, the access time register programming of external devices such as flash memory, SDRAM, and PCMCIA/CF must be adjusted since access times of these external devices are all derived from the CPU clock.

Use these steps to change the clock frequency on the fly (Some of the following only applies to the SA-110.):

           Disabling all devices that would be interrupted during a frequency change.
           Disable clock switching
           Force DCLK to MCLK
           Write the new CCF value to PPCR
           Re-enable clock switching
           Re-enable/reinitialize all devices that were disabled in (1)