SEAT-LA

For Download  of SEAT - LA, email ramanara@cse.psu.edu with your name and contact information.

SEAT-LA is a tool that uses a new approach to model soft errors in logic circuits. It  can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Figure 1 SEAT-LA SER Estimation Methodology

Figure 1 shows our methodology as applied to a logic chain for a specified set of primary inputs. Here, current pulses are injected in each node. The corresponding voltage pulse is obtained by using the values from a current-voltage (I-V) transfer table. Once a corresponding output voltage is obtained, the propagated pulse width and amplitude at the output of each gate along the path are calculated using the equations presented in [1] and the pre-characterized delay models. Since we also account for the state of each node when propagating the pulse, logical masking is accounted for inherently. Once the voltage pulse propagates to the flip-flop, the pulse-width and amplitude values are used to obtain the corresponding tw using the flip-flop characterization table explained later.

Once the tw for a node to one output is known, assuming the probability of a pulse hitting a node N to be PN , which is a factor of area occupied by the node, the pulse size etc., the soft error rate for the output ( for example O in Figure 2), SERO, can be calculated as follows:

SERO = ∑N PN * tw         

Thus if the circuit has m outputs, the overall SER is:

SER = ∑m SERO               

SEAT-LA Tool Flow   Implementation

Figure 3 shows the SEAT-LA tool implemented as a part of the bigger tool flow. The tool was implemented using perl and Tcl scripts to work in conjunction with other required tools. As can be seen from Figure 2, the back annotated gate level net-list is taken as an input. Design compiler is used to extract the paths from each node to the output. The tool also requires the capacitance at each node using which the delay and slope tables are to be indexed. These capacitances were obtained from the back annotated net-lists. The state of each node was obtained for a given input vector using the model-sim simulator. Once the state of every node is obtained, SEAT-LA (in Figure. 2) computes the pulse propagation from each node to the output and finds the tw as explained in the previous section. This analysis is done for each path of every node. Thus, as described in previous section, the SER is obtained by summing up the tw for all nodes in the path.

For complete details, please refer to

• R.Rajaraman, J.S. Kim,N. Vijaykrishnan,Y.  Xie,M.J. Irwin, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic", in the Proc. of 19th International Conference on VLSI Design, January 2006, Hyderabad, India.

 

* This work is supported in part by NSF Award # 0454123