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Publications Produced by the Soft Error Research

Journals:

  • R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie and M. J. Irwin,   Modeling Soft Errors at Device and Logic Level for combinational circuits  , Under review at Transactions on Dependable and Secure Computing.
  • V. Degalahal, L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin,  Soft Errors in Low Power Caches  IEEE Transactions on VLSI Systems, Volume 13,  Issue 10,  Oct. 2005 Page(s):1157 - 1166.
  • V. Degalahal, R. Rajaraman, N. Vijaykrishnan, Y. Xie and M. J Irwin,  Effect of Power Optimization on Soft Error Rate in Logic circuits , invited book chapter for VLSI-SOC book of select papers.
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin,  Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy  ',  ACM Transactions on Architecture and Code Optimization (TACO),  Volume 1 ,  Issue 1  (March 2004),  Pages: 3 - 33.

 

Conferences:

  • K.Ramakrishnan, R.Rajaraman, S.Suresh, N. Vijaykrishnan, Y. Xie & M.J.Irwin,  Variation Impact on SER of Combinational Circuits , In the Proc. of 8th International Conference on Quality Electronic Design (ISQED), pp. 911-916, 2007.
  • Feng Wang, Yuan Xie, R. Rajaraman & B. Vaidyanathan  Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model  In the Proc. of International Conference on VLSI Design (VLSID) , pp. 165-170, Bangalore, 2007.
  • K. Ramakrishnan, S. Suresh, N. Vijaykrishnan, M. J. Irwin,  Impact of NBTI on FPGAs , In the Proc. of International Conference on VLSI Design (VLSID) , pp. 717-722, Bangalore, 2007.
  • R.Rajaraman, K. Ramakrishnan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "Temperature and Voltage  Scaling effects on Electrical Masking", in the Proc. of Workshop on System Effects of Logic Soft Errors (SELSE), 2006.
  • Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo,  Dependability Analysis of Nano-scale FinFET circuits   in the Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 399-404, 2006.
  • R.Rajaraman, J.S. Kim,N. Vijaykrishnan,Y.  Xie,M.J. Irwin, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic", In the Proc. of 19th International Conference on VLSI Design (VLSID), pp. 499-502, January 2006, Hyderabad, India.
  • J. S. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. "Compiler-Directed Instruction Duplication for Soft Error Detection". in Proc. of the Conference on Design, Automation and Test in Europe (DATE'05), pp. 1056-1057, Munich, Germany, March 7-11, 2005.
  • S. Yang, W.Wolf, W.Wang, N.Vijaykrishnan, and Y. Xie, "Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies", in the Proc. of Asia South Pacific Design Automation Conference ASPDAC),pp. 539-544, China 2005.
  • S. Sundar, S. Kanth, V. Chandrasekhar, S. Srinivasan, N. Vijaykrishnan and V. Kamakoti. "A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs." The 2004 International Conference on Field Programmable Technology, Dec 2004.
  • Yuan Xie, Lin Li, Mahmut Kandemir, N. Vijaykrishnan, and Mary Jane Irwin, "Reliability-Aware Co-synthesis for Embedded Systems", in Proc. of IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP'04), September 2004
  • S.Srinivasan, A.Gayasen, N.Vijaykrishnan, M.Kandemir, Y.Xie, M.J.Irwin, "Improving Soft-error Tolerance of FPGA Configuration Bits", in the Proc. of the International Conference on Computer Aided Design (ICCAD-04) , pp. 107-110, Nov 2004.
  • K. Unlu, V. Degalahal, M. S. Cetiner, N. Vijaykrishnan and M.J Irwin,  "Testing Neutron- Induced Soft Errors in Semiconductors ", in the Proc. of ANS Winter mtgs., to held in Washington DC, Nov 2004.
  • V. Degalahal, S. Cetiner, F. Alim, N. Vijaykrishnan, K. Unlu and M. J. Irwin, ``SESEE: Soft Error Simulation and Estimation Engine'', 2004 MAPLD International Conference October 2004, at Washington DC.
  • Rajaraman Ramanarayanan, N. Vijaykrishnan, Yuan Xie and Mary Jane Irwin, and Kerry Bernstein, "Soft Errors in Adder Circuits", in the 2004 MAPLD Washinton DC, Sept 2004.
  • L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, ``Soft Error and Energy Consumption Interactions: A Data Cache Perspective'',  in the Proc. of International Symposium for Low Power Electronics and Design (ISLPED), pp. 132-137, May 2004  Newport.
  • V. Degalahal, R. Rajaram, N. Vijaykrishanan, Y. Xie , M. J Irwin, "The effect of threshold voltages on soft error rate", in the Proc. 5th International Symposium on Quality Electronic Design (ISQED), March 22-24, 2004 at San Jose, California. Page (s): 503-508 (Presentation)
  • R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J Irwin, D. Duarte, "Analysis of Soft-Error Rate for Flip-Flops and Scannable Latches", in Proc of IEEE International SOC Conference, 2003,Portland, Oregon., Pages (s): Pages:231 - 234 ( Presentation)
  • V. Degalahal, N. Vijaykrishnan, M.J Irwin,  "Analyzing Soft Errors in Leakage Optimized SRAM Design" , in the Proc. of 16th International Conference on VLSI Design, January 2003, New Delhi, India. Page (s): 227 -233 (Presentation)


      * This work is supported in part by NSF Award # 0454123

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