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2005 Publications

Reducing Power with Performance Constraints for Parallel Sparse Applications

Citation: Reducing Power with Performance Constraints for Parallel Sparse Applications; G. Chen, K. Malkowski, M. Kandemir, and P. Raghavan; Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12; p 231.1; 2005.

Summary: We reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties. Our experiments with matrices extracted from real applications indicate that our recursive strategies are very effective in saving power, and the savings achieved are close to the optimal values.

Abstract: Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computation-to-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes and evaluates different schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties. The experiments with matrices extracted from real applications as well as with model matrices indicate that the proposed strategies are very effective in saving power, and the savings achieved come close to the optimal limits. Our results also show that the proposed approach can also be used to study power-performance tradeoffs in environments where certain performance degradation is tolerable.

Availability: This paper is available at this site: ipdps05.pdf. The conference site is http://www.ipdps.org/.

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