RAS Papers 2006
CSE MDL Reliable Circuits and Systems papers of 2006
- R.Rajaraman, K. Ramakrishnan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "Temperature and Voltage Scaling effects on Electrical Masking", in the Proc. of Workshop on System Effects of Logic Soft Errors (SELSE), April 2006. paper.pdf
- Ing-chao Lin, Suresh Srinivasan, Vijaykrishnan Narayanan, Nagu Dhanwada, Transaction Level Error Susceptibility Model for Bus Based SoC? Architectures, Proc. of Inter. Symposium on Quality Electronic Design (ISQED), March 2006. ISQED06.pdf
- Suresh Srinivasan and Vijaykrishnan Narayanan, Variation Aware Placement in FPGAs, Proc. of the Symposium on VLSI, March 2006. PDF:
- G. Chen, G. Chen, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Object duplication for improving reliability. In Proc. the 11th Asia and South Pacific Design Automation Conference, Yokohama City, Japan, January 2006.
- G. Chen, M. Kandemir, and F. Li. Energy-aware computation duplication for improving reliability in embedded chip multiprocessors. In Proc. the 11th Asia and South Pacific Design Automation Conference, Yokohama City, Japan, January 2006.
- R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin, SEAT-LA: A Soft Error Analysis Tool for Combinational Logic, in the Proc. of the Inter. Conf. on VLSI Design, Jan. 2006. paper.pdf
- S. H. K. Narayanan, M. Kandemir, R. Brooks, I. Kolcu. Secure Execution of Computations on Untrusted Hosts, in the proceedings of ADA-Europe 2006. PDF PPT.
- Conferred the Best Presentation Award at the conference JPG.
- Suresh Srinivasan, Prasanth Mangalagiri, Karthik Sarpatwari, Yuan Xie and Vijaykrishnan Narayanan, FLAW: FPGA Lifetime AWareness, Proc. of Design Automation Conference (DAC), July 2006. PDF:
- Suresh Srinivasan, Raghavan Ramadoss and Vijaykrishnan Narayanan. Process Variation Aware Parallelization Strategies in MPSoCs?, To appear in Proc. of IEEE International SOC Conference, Sept 2006. PDF:
- D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan and C.R. Das, Exploring Fault-Tolerant Network-on-Chip Architectures, in Proceedings of the International Conference on Dependable Systems and Networks (DSN), pp. 93-102, 2006. PDF