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RAS Papers 2005

CSE MDL Reliable Circuits and Systems papers of 2005

  • V. Degalahal, L. Li, N. Vijaykrishnan, M. Kandemir,M. J. Irwin, Soft Errors Issues in Low Power Caches, to appear in IEEE Trans. on VLSI.
  • M. Srinivasan, T. Theocharides, L. Benini, G. DeMicheli, N. Vijaykrishnan, M. J. Irwin, Analysis of Error Recovery Schemes for Networks-On-Chips, to appear in IEEE Design and Test of Computers, Special Issue on Networks on Chips.
  • G. Chen and M. Kandemir. Runtime integrity checking for inter-object connections. In Proc. International Conference on Computer Aided Design, pp. 303-306, San Jose, California, November 2005.
  • EJ. Kim, D. Park, C. Nicopoulus, N. Vijaykrishnan, C. Das, Design and Analysis of an NoC Architecture from Performance, Reliability and Energy Perspective, to appear in Proc. of 1st Symp. on Architectures for Networking and Communication Systems, Oct. 2005.
  • G. Chen, M. Kandemir, and M. Karakoy. Memory space conscious loop iteration duplication for reliable execution. In Proc. the 12th International Static Analysis Symposium, pp. 52-69, London, UK, September 2005.
  • G. Chen, M. Kandemir, and M. Karakoy. A data-centric approach to checksum reuse for array-intensive applications. In Proc. the International Conference on Dependable Systems and Networks, pp. 316-325, Yokohama, Japan, June 28 - July 1, 2005.
  • S. Reddy, V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan, A CLB Architecture for Online Correction of SEU-based Errors in LUTs of SRAM-based FPGAs, Proc. of the European Test Symposium, May 2005.
  • S. Reddy, V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan, Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration, Proc. of the European Test Symposium, May 2005.
  • S. Reddy, V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan, Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs, Proc. of the 12th Reconfigurable Architectures Workshop, pp. 172a, Apr. 2005.
  • J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, Compiler-directed Instruction Duplication for Soft Error Detection, Proc. of DATE’05, pp. 1056-1057, Mar. 2005.
  • S. Sundar, V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan, Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs, Proc. of ASP-DAC’05, Jan. 2005.
  • Sri Hari Krishna N. , Seung Woo Son, Mahmut Kandemir, Feihui Li, Using Loop Invariants to Fight Soft Errors in Data Caches, in Proc. of ASP-DAC’05, Jan. 2005. PDF PPT Poster-PPT
  • G. Chen, M. Kandemir, M. J. Irwin, Compiler-directed Selective Data Protection Against Soft Errors, Proc. of ASP-DAC’05, Jan. 2005.
  • S. Sundar¸ M. Sashikanth, V. Chandrasekhar, N. Vijaykrishnan, V. Kamakoti, Detecting SEU-caused Routing Errors in SRAM-based FPGAs, Proc. of the 18th Conference on VLSI Design, pp. 736-741, Jan. 2005.
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