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PAS Papers 2006

CSE MDL Temperature and Power Aware Systems Publications of 2006

  • Wei-lun Hung, Xiaoxia Wu, Yuan Xie, Guaranteeing Performance Yield in High-Level Synthesis, IEEE International Conference on Computer Aids Design, 2006.
  • Xiaoxia Wu, Feng Wang, Yuan Xie, Analysis of Sub-threshold FINFET Circuits for Ultra-low Power Design, IEEE International SOC Conference, 2006
  • V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin, Effect of Power Optimizations on Soft Error Rate, to appear in IFIP Series on VLSI-SoC, Ed. by Reis.
  • M. Kandemir, J. Ramanujam, U. Sezer, Improving the Energy behavior of Block Buffering Using Compiler Optimizations, to appear in ACM Transactions on Design Automation of Electronic Systems.
  • W. Zhang, Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Reducing Dynamic and Leakage Energy in VLIW Architectures, to appear in ACM Trans. on Embedded Computing Systems, Special Issue on Power-Aware Embedded Computing.
  • W. Zhang, M. Kandemir, M. Karakoy, G. Chen, Reducing Data Cache Leakage Energy using a Compiler-based Approach, to appear in ACM Transactions on Embedded Computer Systems.
  • S. Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Energy-Efficient Java Execution Using Local Memory and Object Co-location, to appear in IEE Proceedings: Computers and Digital Techniques.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang, Masking the Energy Behavior of Encryption Algorithms, to appear in IEE Proceedings: Computers and Digital Techniques.
  • H. Koc, O. Ozturk, M. Kandemir, Sri H. K. Narayanan and E. Ercanli. Minimizing Energy Consumption of Banked Memories Using Data Recomputation, in the Proc. of ISLPED'06. PDF PPT.
  • M. Mutyam, F. Li, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, Compiler-Directed Thermal Management for VLIW Functional Units, Proc. of LCTES’06, pp. 163-172, Jun. 2006.
  • M. Mutyam, M. Eze, N. Vijaykrishnan, and Y. Xie, Delay and Energy Efficient Data Transmission for On-Chip Buses, Proc. of the Symposium on VLSI, 2006.
  • Sri Hari Krishna Narayanan, Mahmut Kandemir, Ozcan Ozturk, Compiler-Directed Power Density Reduction in NoC Based Multi-Core Designs, Proceedings of ISQED, Mar. 2006.
  • F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin, On-chip Bus Thermal Analysis and Optimization, Proc. of DATE’06, Vol. 1, 6 pages, Mar. 2006. presentation PDF PPT
  • T. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, V. Degalahal, A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks, 19th Inter. Conf. on VLSI Design, Jan. 2006. PDF
  • C.A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M.S. Yousif and C.R. Das, ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers, in Proceedings of the 39th Annual International Symposium on Microarchitecture (MICRO), pp. 333-344, 2006. PDF
  • D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, C.R. Das, A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects, in Proceedings (electronic) of the International Conference on Nano-Networks (Nano-Net), 2006. PDF
  • F. Li, C.A. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan and M. Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, in Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, 2006. PDF
  • J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, M.S. Yousif and C.R. Das, A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks, in Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA), pp. 4-15, 2006. PDF
  • J. Kim, D. Park, C.A. Nicopoulos, N. Vijaykrishnan and C.R. Das, Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures, in Special Workshop on Future Interconnects and Networks on Chip at the Design, Automation and Test in Europe (DATE) Conference, 2006.
  • Suresh Srinivasan, Raghavan Ramadoss and Vijaykrishnan N. Process Variation Aware Parallelization Strategies in MPSoC. In proceedings of 19th IEEE International SOC Conference (SOCC), Austin, Texas, Sept. 2006. PDF


  • Suresh Srinivasan, Prasanth Mangalagiri, Karthik Sarpatwari, Yuan Xie and Vijaykrishnan N. FLAW: FPGA Lifetime Awareness. In Proceedings of Design Automation Conference (DAC), San Francisco, July 2006. PDF PPT


  • Suresh Srinivasan and Vijaykrishnan N. Variation Aware Placement in FPGAs. In proceedings of IEEE Computer Society Annual Symposium on VLSI(ISVLSI), Karlsruhe, Germany, March 2006. PDF PPT


  • Ing-Chao lin, Suresh Srinivasan, Nagu R. Dhanwada, and Vijaykrishnan N. Transaction level error susceptibility model for bus based SoC? architectures. In proceedings of International Symposium on Quality Electronic Design (ISQED), 2006.
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