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CSE MDL Temperature and Power Aware Systems Publications of 2003

  • N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N. Vijaykrishnan, Leakage Current: Moore's Law Meets Static Power, IEEE Computer, Special Issue on Power and Temperature-Aware Computing, 36(12):68-75, Dec. 2003.
  • U. Sezer, G. Chen, M. Kandemir, H. Saputra, M. J. Irwin, Exploiting Bank Locality in Multi-bank Memories, Proc. of CASES'03, pp. 287-297, Oct 2003.
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, B. Mathiske, M. Wolczko, Heap Compression for Memory-constrained Java Environments, Proc. of the 18th Conf. on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'03), pp. 282-301, Oct. 2003.
  • V. De La Luz, A. Sivasubramaniam, M. Kandemir, M. J. Irwin, N. Vijaykrishnan, Reducing dTLB Energy Through Dynamic Resizing, Proc. of ICCD’03, pp. 358-363, Oct. 2003.
  • V. De La Luz, M. Kandemir, G. Chen, M. J. Irwin, I. Kolcu, Energy-conscious Memory Allocation and Deallocation for Pointer-intensive Applications, Proc. of the 3rd Conf. on Embedded Software (EMSOFT'03), pp. 156-172, Oct 2003.
  • G. Chen, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, M. Wolczko, Tracking Object Life Cycle for Leakage Energy Optimization, Proc. of ISSS/CODES’03, pp. 213-218, Oct. 2003.
  • A. Hegde, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Variable Line Sized Cached DRAMs, Proc. of ISSS/CODES’03, pp. 132-137, Oct. 2003.
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin, Energy and Timing Characterization of VLSI Charge-pump Phase-locked Loops, Proc. of ASIC/SOC'03, pp. 341-344, Sep 2003.
  • G. Chen, Guangyu Chen, M. Kandemir, N. Vijaykrishnan, M. J. Iwin, Energy-Aware Code Cache Management for Memory-Constrained Java Devices, Proc. of SOC Conf. (ASIC/SOC’03), pp. 179-182, Sep 2003.
  • L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, I. Kadayif, CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors, Proc. of EUROMICRO Symp. on Digital System Design, Architectures, Methods and Tools (DSD'03), pp. 41-48, Sep 2003.
  • V. Delaluz, M. Kandemir, A. Sivasubramaniam, M.J. Irwin, N. Vijaykrishnan, Reducing dTLB Energy Through Dynamic Resizing, Proc. of ICCD’03, Sep. 2003.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang, Masking the Energy Behavior of Encryption Algorithms, IEE Proceedings: Computers and Digital Techniques, 150(5):274-284, Sep. 2003. (Invited among best papers at DATE 2003).
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, R. Brooks, M.J Irwin, Exploiting Value Locality for Secure-Energy Aware Communication, Proc. of SiPS'03, pp. 116-121, Aug. 2003.
  • E. J. Kim, K. H. Yum, G. M. Link, C. R. Das, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Energy Optimization Techniques in Cluster Interconnects, Proc. of ISLPED'03, pp. 459-464, Aug. 2003.
  • J. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir, Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management, Proc. of ISLPED'03, pp. 402-407, Aug. 2003.
  • S. Kim, N. Vijaykrishnan, M. J. Irwin, L. K. John, On Load Latency in Low-Power Caches, Proc. of ISLPED'03, pp. 258-261, Aug. 2003.
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, M. J. Irwin, Estimating Influence of Data Layout Optimizations on SDRAM Energy Consumption, Proc. of ISLPED'03, pp. 40-43, Aug 2003.
  • A. Bhatkar, R. Chandramouli, N. Vijaykrishnan, M. J. Irwin, Computation and Transmission Energy Modeling Through Profiling For MPEG4 Video Transmission, Proc. of Multimedia & Expo, pp. 281-284, July 2003.
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Adapting Instruction Level Parallelism for Optimizing Leakage in VLIW Architectures, Proc. of LCTES’03, pp. 275-283, June 2003.
  • Y-F Tsai, D. Duarte, N. Vijaykrishnan, M. J. Irwin, Implications of Technology Scaling on Leakage Reduction Techniques, Proc. of 40th DAC, pp. 187-190, June 2003.
  • S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, Partitioned Instruction Cache Architecture For Energy Efficiency, ACM Trans. on Embedded Computing Systems, 2(2):163-185, May 2003.
  • G. Chen, B. T. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli, Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices, Proc. of IPDPS'03, (CD-ROM), Apr. 2003.
  • S. Gurumurthi, N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries, Proc. of the IPDPS'03, (CD-ROM), Apr. 2003.
  • M. Kandemir, M. J. Irwin, G. Chen, J. Ramanujam, Address Register Assignment for Reducing Code Size, Proc. of 12th Conf. on Compiler Construction (CC'03), Springer-Verlag LNCS 2622:273-289, Apr. 2003.
  • W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De, Compiler Support for Reducing Leakage Energy Consumption, Proc. of DATE’03, pp. 11146-11147, Mar. 2003.
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang, Masking the Energy Behavior of DES Encryption, Proc. of DATE’03, pp. 10084-10089, Mar. 2003.
  • S. Gurumurthi, J. Zhang, A. Sivasubramaniam, M. Kandemir, H. Franke, N. Vijaykrishnan, M. J. Irwin, Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads, Proc. of the Symp. on Performance Analysis of Systems and Software (ISPASS'03), pp. 123-132, Mar. 2003.
  • L. Li, I. Kadayif, Y-F Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam, Managing Leakage Energy in Cache Hierarchies, Journal of Instruction-Level Parallelism, Vol. 5, Feb. 2003.
  • J. Hu, N. Vijaykrishnan, M. J. Irwin, M. Kandemir, Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch, Proc. ISVLSI'03, pp. 127-132, Feb. 2003.
  • N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Kim, W. Ye, Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework, IEEE Trans. on Computers, 52(1):59-76, Jan. 2003.
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin, A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations, IEEE Trans. on VLSI Systems, 10(6):844-855, Dec. 2002. IEEE/CAS Best Paper Award Winner.
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