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CSE MDL Temperature and Power Aware Systems Publications of prior to 2000

- Y. Zhang, M. J. Irwin, Power and Performance Characteristics of Crossbars and Buses in On-Chip Interconnect Structures,
*Proc. of 33rd Asilomar Conf. on Signals, Systems, and Computers*, Oct. 1999. - W. Ye, K. Li, M. Cheng, M. J. Irwin, Power Characterization of Functional Units,
*Proc. of 33rd Asilomar Conf. on Signals, Systems, and Computers*, Oct. 1999. - M. J. Irwin, N. Vijaykrishnan, Energy Issues in Multimedia Systems, Invited,
*Proc. of SiPS’99*, pp. 24-33, Oct. 1999. - Y. Wu, M. J. Irwin, Power Analysis of Gated Pipeline Registers,
*Proc. of ASIC’99*, pp. 281-285, Sept. 1999. - B. Bishop, M. J. Irwin, Databus Charge Recovery: Practical Considerations,
*Proc. of ISLPED’99*, pp. 85-87, Aug. 1999. - M. J. Irwin, N. Vijaykrishnan, A Transition Sensitive, Architectural Level Power Analysis Approach, IEEE Computer Society
*TCVLSI Technical Bulletin*, pp. 6-11, Summer 1999. - R. Chen, N. Vijaykrishnan, M. J. Irwin, Clock Power Issues in Systems-on-a-Chip Designs,
*Proc. of WVLSI’99*, pp. 48-53, Apr. 1999. - Y. Zhang, M. J. Irwin, Energy-Delay Analysis for On-Chip Interconnect at the System Level,
*Proc. of Workshop on VLSI*(WVLSI), pp. 26-31, Apr. 1999. - Y. Zhang, W. Ye, M. J. Irwin, An Alternative Architecture for On Chip Global Interconnect: Segmented Bus Power Modeling,
*Proc. of 32nd Asilomar Conf. on Signals, Systems, and Computers*, pp. 1062-1065, Nov. 1998. - J. Sacha, M. J. Irwin, Number Representations for Reducing Data Bus Power Dissipation,
*Proc. of 32nd Asilomar Conf. on Signals, Systems, and Computers*, pp. 213-217, Nov. 1998. - J. Sacha, M. J. Irwin, Input Recoding for Reducing Power in Distributed Arithmetic,
*Proc. of SiPS’98*, pp. 599-608, Oct. 1998. - Y. Zhang, W. Ye, R. Chen, M. J. Irwin, System Level Interconnect Power Modeling,
*Proc. of ASIC’98*, pp. 289-293, Sept. 1998. - R. Chen, M. J. Irwin, R. Bajwa, Architectural Level Hierarchical Power Estimation of Control,
*Proc. of ASIC’98*, pp. 211-215, Sept. 1998. - J. Sacha, M. J. Irwin, The Logarithmic Number System for Strength Reduction in Adaptive Filtering,
*Proc. of ISLPED’98*, pp. 256-261, Aug 1998. - R. Chen, M. J. Irwin, R. Bajwa, An Architectural Level Power Estimator,
*Proc. of the Power-Driven Microarchitecture Workshop*, held in conjunction with ISCA’98, pp. 87-91, June 1998. - R. Chen, M. J. Irwin, R. M. Owens, R. Bajwa, Validation of an Architectural Level Power Analysis Technique,
*Proc. of 35th DAC*, pp. 242-245, June 1998. - J. Sacha, M. J. Irwin, Number Representations for Reduced Switched Capacitance in Subband Coding,
*Proc. of ICASSP’98*, May 1998. - E. Gayles, K. Acken, R. M. Owens, M. J. Irwin, A Robust CMOS Logic
Technique for Building High Frequency Circuits with Efficient
Pipelining,
*Proc. of ASIC’97*, pp. 168-172, Sept. 1997. - Y. Zhang, W. Ye, R. M. Owens, M. J. Irwin, The Power Analysis of Interconnects,
*Proc. of ASIC’97*, pp. 25-29, Sept. 1997. - H. Mehta, R. M. Owens, M. J. Irwin, Techniques for Low Energy Software,
*Proc. of ISLPED’97*, pp. 72-75, Aug 1997. - A. Kalambur, M. J. Irwin, An Extended Addressing Mode for Low Power,
*Proc. of ISLPED’97*, pp. 208-213, Aug. 1997. - E. Gayles, K. Acken, R. M. Owens, M. J. Irwin, A Clocked, Static
Circuit Technique for Building Efficient High Frequency Pipelines,
*Proc. of GLSVLSI’97*, pp. 182-187, March 1997. - M-F Chang, M. J. Irwin, R. M. Owens, Power-Area Trade-Offs in Memory Arrays with Dual Word Lines,
*Journal of Circuits, Systems, and Computers*, special issue on Applications of Low Power Design, 7(1):49-67, Feb. 1997. - H. Mehta, R. M. Owens, M. J. Irwin, A Simulation Methodology for Software Energy Evaluation,
*Proc. of VLSI’97*, pp. 509-510, Jan. 1997. - C. Nagendra, M. J. Irwin, R. M. Owens, Area Time Power Tradeoffs in Parallel Adders,
*IEEE Trans. on Circuits and Systems*, 43(10):689-702, Oct. 1996. - E. Gayles, R. M. Owens, M. J. Irwin, A Fast Compact Addition Architecture for Low Power Microprocessors and DSP Chips,
*Proc. of Conf.on VLSI Systems Solutions*, pp. 41-44, Sept. 1996. - E. Gayles, R. M. Owens, M. J. Irwin, Low Power Circuit Techniques for Fast Carry-Skip Adders,
*Proc. of 1996 Midwest Symp. on Circuits and Systems*, pp. 87-90, Aug. 1996. - K. Acken, M. J. Irwin, R. M. Owens, Power Comparisons for Barrel Shifters,
*Proc. of the Symp. on Low Power Electronics and Design*(ISLPED), pp. 209-214, Aug. 1996. - M. Borah, R. M. Owens, M. J. Irwin, Transistor Sizing for Low Power CMOS Circuits,
*IEEE Trans. on CAD*, 15(6):665- 571, June 1996. - H. Mehta, R. M. Owens, M. J. Irwin, Energy Characterization Based on Clustering,
*Proc. of 33rd DAC*, pp. 702-707, June 1996. - H. Mehta, R. M. Owens, M. J. Irwin, Instruction-Level Power Profiling,
*Proc. of ICASSP’96*, pp. 6:3327-3330, May 1996. - H. Mehta, R. M. Owens, M. J. Irwin, Some Issues in Gray Code Addressing,
*Proc. of the GLSVLSI’96*, pp. 178-181, March 1996. - C. Nagendra, R. M. Owens, M. J. Irwin, Low Power Considerations in the Design of Pipelined FIR Filters,
*Proc. of the IEEE Symp. on Low Power Electronics*, pp. 32-33, Oct. 1995. - H. Mehta, R. M. Owens, M. J. Irwin, Small Signal Model for Low Power DSP,
*Proc. of the IEEE Symp. on Low Power Electronics*, pp. 28-29, Oct. 1995. - H. Mehta, M. Borah, R. M. Owens, M. J. Irwin, Accurate Estimation of Combinational Switching Activity,
*Proc. of 32nd DAC*, pp. 618-622, June 1995. - M. Borah, R. M. Owens, M. J. Irwin, Transistor Sizing for
Minimizing Power Consumption of CMOS Circuits under Delay Constraints,
*Proc. of ISLPD’95*, pp. 167-172, April 1995. - M. Borah, R. M. Owens, M. J. Irwin, High-Throughput and Low-Power DSP Using Clocked-CMOS Circuitry,
*Proc. of ISLPD’95*, pp. 139-144, April 1995. - C. Nagendra, R. M. Owens, M. J. Irwin, Unifying Carry-Sum and Signed-Digit Number Representations for Low Power,
*Proc. of Symp. on Low Power Design*(ISLPD), pp. 15-20, April 1995. - M. Borah, M. J. Irwin, R. M. Owens, Minimizing Power Consumption
of Static CMOS Circuits by Transistor Sizing and Input Reordering,
*Proc. of VLSI'95*, pp. 294-298, Jan. 1995. - C. Nagendra, M. J. Irwin, R. M. Owens, Low Power Tradeoffs in Signal Processing Hardware Primitives, in
*VLSI Signal Processing*, VI, pp. 276-285, Oct. 1994. - C. Nagendra, R. M. Owens, M. J. Irwin, Power-Delay Characteristics of CMOS Adders,
*IEEE Trans. on VLSI Systems*, 2(3):377-381, Sept. 1994. Also appeared in*High Performance Systems Design*, Ed. V. Oklobdzija, IEEE Press, July 1999. - C. Nagendra, H. Mehta, R. M. Owens, M. J. Irwin, A Comparison of the Power-Delay Characteristics of CMOS Adders,
*Proc. of orkshop on Low Power Design*, pp. 231-236, April 1994.