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Yuan Xie
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Yuan Xie

  • Associate Professor
354E IST Building
University Park, PA 16802
Phone: (814) 865-7496

Websites:

Education:

  1. Ph.D., Princeton University

Biography:

Professor Yuan Xie is a faculty member in Computer Science and Engineering department at Penn State. He received the B.S. degree in electronic engineering from Tsinghua University and received the M.S. and Ph.D. degrees in electrical engineering from Princeton University. Before joining Penn State in fall 2003, he was with IBM Microelectronic Division's Worldwide Design Center.


He was a recipient of the NSF CAREER award in 2006 and the SRC Inventor Recognition Award in 2002. He also received Best Paper Award at the International Conference on ASICs 2001 and the Best Paper Award Nomination at the International Conference on Computer Aided Design 2006. He is currently associate editor for IEEE Transactions on VLSI. His research interests include VLSI design, computer architecture, embedded systems design, and EDA.

Research Interests:

VLSI Design, Computer Architecture, Embedded Systems Design, Electronics Design Automation

Selected Publications:

  1. Li, F., C. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan, M. Kandemir. June 2006. Design and Management of 3D Chip Multiprocessors using Network-in-memory. Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA'06). pp. 130-141. Boston, MA.
  2. Xie, Y., G. Loh, B. Black, K. Bernstein. April 2006. Design Space Exploration for 3D Architecture. ACM Journal of Emerging Technologies for Computer Systems 2(2):65-103.
  3. Tsai, Y-F., Y. Xie, N. Vijaykrishnan, M. J. Irwin. October 2005. Three-Dimensional Cache Design Exploration Using 3DCacti. Proceedings of the IEEE International Conference on Computer Design (ICCD 2005). pp. 519-524. San Jose, CA.
  4. Xie, Y., J. Xu, W. Wolf. April 2003. Augmenting Platform-based Design with Synthesis Tools. Journal of Circuits, Systems and Computers 12(2):125-142.
  5. Xie, Y., W. Wolf, H. Lekatsas. December 2001. A Code Decompression Architecture for VLIW Processors. Proceedings of the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. Austin, TX.