Aditya Yanamandra

I am a Doctoral student in the Microsystems Design Laboratory at the Computer Science and Engineering Department at Penn State. Prior to this, I completed my undergraduate studies in Computer Science and Engineering at the Indian Institute of Technology, Madras.

Journal Articles

• "On the Effects of Process Variation in Network-on-Chip Architectures," C.A. Nicopoulos, S. Srinivasan, Aditya Yanamandra, D. Park, N. Vijaykrishnan, C.R. Das, and M.J. Irwin, IEEE Transactions on Dependable and Secure Computing (TDSC).

Conference Proceedings

• "In-Network Caching for Chip Multiprocessors," Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut Kandemir, Sri Hari Krishna Narayanan. HiPEAC'09, Jan 2009
• "Evaluating the Role of Scratchpad Memories in Chip Multiprocessors for Sparse Matrix Computations," Aditya Yanamandra, Bryan Cover, Padma Raghavan, Mary Jane Irwin, Mahmut Kandemir. IPDPS'08, April 2008
• "Analysis and Solutions to Issue Queue Process Variation," N.Soundararajan, Aditya Yanamandra, C.A. Nicopolous, N. Vijaykrishnan, Anand Sivasubramaniam and Mary Jane Irwin. DSN'08, June 2008
• "Variation-Aware Low-Power Buffer Design," C.A Nicopoulos, Aditya Yanamandra, S. Srinivasan, N. Vijaykrishnan, M. J. Irwin. ASILOMAR'07, November 2007.
• "A Low-Power Phase Change Memory Based Hybrid Cache Architecture," P. Mangalagiri, K. Sarpatwari, Aditya Yanamandra, N. Vijaykrishnan, O. Awadelkarim, Yuan Xie and Mary Jane Irwin. GLSVLSI'08 (short paper), May 2008
• "Evaluating the role of scratchpad memories in multi-cores for sparse matrix computations," Aditya Yanamandra, Bryan Cover, Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, Mary Jane Irwin. SC07 (poster), November 2007.